Senior Digital Systems Architect

2 days ago

Alleppey, Kerala, India beBeeDesign Full time ₹ 1,60,00,000 - ₹ 2,40,00,000
About this Role

As a highly skilled RTL Principal Design Engineer, you will be responsible for leading the development of complex IP solutions. Your expertise in Verilog and System Verilog will enable you to design and implement cutting-edge technologies.

This role involves working with cross-functional teams to develop high-performance, low-power RTL designs. Your knowledge of PCIe/CXL/IDE protocols will be invaluable in ensuring seamless integration with existing systems.

  • You will lead the design and verification efforts for the Interface Controller IP team.
  • Your responsibilities will include creating new features, collaborating with engineers, and ensuring that all designs meet the required standards.
Requirements

To succeed in this position, you will need:

  • A Bachelor's degree in Electrical/Electronics/VLSI Engineering or related field.
  • 8-16 years of experience in RTL Design using Verilog, with a focus on system-level design.
  • Familiarity with UVM-based environments and System Verilog is essential.
  • Experience with PCIe/CXL/IDE protocols and implementation of complex protocols is a must.
What We Offer

In addition to a competitive compensation package, we offer:

  • A dynamic work environment with opportunities for growth and professional development.
  • The chance to work with a talented team of engineers and contribute to cutting-edge projects.
  • A comprehensive benefits package, including health insurance, retirement savings plan, and paid time off.

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