
Expert ASIC Design Timing Closure Specialist
5 days ago
Eteros Technologies is a Semiconductor Engineering services startup.
We work on cutting-edge technology nodes while working on state-of-the-art designs in AI/ML, Datacenter, Automotive, and 5G domains.
Our engineers work with some of the brightest, innovative, and successful engineers and leaders around the world.
We are not your traditional design services company offering staff augmentation. Our engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery.
We invest in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge.
Synthesis and Static Timing Analysis Role
You will lead the synthesis, static timing, and DFT efforts for an advanced mixed-signal chip.
This highly visible role requires thorough knowledge of the ASIC design timing closure flow and methodology.
Key Responsibilities Include:
- Full chip and block level timing closure ownership throughout the entire project cycle.
- Develop and maintain methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
- Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.
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