Senior Chip Architectural Designer

1 week ago

Hyderabad Secunderabad Telangana, India beBeePhysicalDesignEngineer Full time US$ 1,50,000 - US$ 2,00,000
Job Description

The position involves collaboration with a seasoned physical design team to deliver tile and FullChip designs that meet stringent requirements for frequency, power, and other design parameters. This is a fast-paced environment working with cutting-edge technology.

We are seeking an experienced professional who possesses strong analytical and problem-solving skills, excellent communication and presentation abilities, and a good attitude towards new challenges.

  • Roadmap from RTL to GDSII flow
  • Floor-plan implementation, Physical Design of Power-plan, Synthesis, Placement, CTS, Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR
  • Timing analysis setup and signoff for multi-corner multi-voltage designs; Hierarchical timing analysis and convergence at block, section, and fullchip levels.
  • Closely engaging with Design teams to understand the design, constraints, and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations.
  • Utilizing different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Identifying and implementing opportunities for improving PPA
Required Skills and Qualifications
  • 16+ years of professional experience in physical design, full chip timing, and preferably with high-performance designs
  • Experience in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc.), Timing ECOs, PV/Noise modelling, .libs, is a must
  • Experience in automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications
  • Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
  • Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
  • Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
  • Versatility with scripts to automate design flow. Proficiency in scripting language, such as Perl and Tcl
  • Strong communication skills, ability to multitask across projects, and work with geographically spread out teams
  • Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm
  • Excellent physical design and timing background
  • Good understanding of computer organization/architecture is preferred
  • Strong analytical/problem solving skills and pronounced attention to details
Benefits
  • Possibility of growth within the company
  • Chance to work on challenging projects
  • Opportunity to be part of a talented team
Others
  • Qualification: Bachelor or Master's degree in Electronics/Electrical Engineering

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