Senior Chip Designer Lead

24 hours ago

Greater Hyderabad Area, India beBeeChipDesigner Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

Job Description

We are seeking an experienced professional to lead the development of high-performance chips for complex SoCs in the area of High-Bandwidth Memory (HBM). This is a challenging opportunity for a seasoned chip designer who can drive architectural decisions, oversee multiple design teams, and ensure timely project delivery.

Key Responsibilities:

  • Develop comprehensive chip specifications in collaboration with architect and design leads.
  • Make informed PPA (Power, Performance, and Area) decisions to meet project goals.
  • Establish clear development checkpoints for IP/SoC Design/DV/PD to ensure on-time completion.
  • Create an overall project plan and schedule details for effective team coordination.
  • Work closely with Analog/Digital IP teams to define integration details for the IPs.
  • Oversee the full chip floorplan, providing area/floorplan targets to IP teams.
  • Define sign-off criteria for the device to ensure quality and reliability.
  • Develop a comprehensive SoC verification plan, outlining key scenarios to be covered.
  • Assist/Review the micro architecture definition for digital blocks to ensure accuracy and efficiency.
  • Establish RTL Quality gate criteria for integration – Lint/CDC to ensure high-quality designs.
  • Drive timing constraints/timing analysis/closure activities to meet project deadlines.
  • Define Design-for-Test (DFT) targets for the chip and cascade that into necessary DFT activities.
  • Collaborate with Physical Design engineers to achieve physical design closure.
  • Handle tapeout formalities to ensure seamless project completion.

Qualifications:

  • A minimum of 15 years of solid experience in SoC design.
  • A self-motivated individual ready to take ownership of defining new processes.
  • Able to handle heavy workload while delivering results under tight deadlines.
  • Proven ability to develop architecture and micro-architecture from specifications.
  • Understanding of chip I/O design and packaging is advantageous.
  • Experience in reviewing top-level test plans is beneficial.
  • Expertise in Synopsys Design Compiler for synthesis and formal verification.
  • Strong working knowledge of timing closure processes.
  • Experience with post-silicon bring-up and debugging.
  • Familiarity with SoC integration challenges.
  • Knowledge of design verification aspects is essential.
  • Desirable to have experience from SoC specification to GDS and commercialization.
  • Ability to make timely and effective decisions even with incomplete information.
  • Demonstrated expertise in specific technical areas, with significant experience in related fields.
  • Effective communication and leadership skills to manage small to medium-sized teams.

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