Senior ASIC Design and STA Engineer
1 month ago
NVIDIA is a leader in the field of high-speed communication devices, and we're seeking a talented Senior ASIC Design and STA Engineer to join our team. As a key member of our Networking Silicon engineering team, you'll play a crucial role in developing innovative chips that deliver exceptional performance and efficiency.
Key Responsibilities:
- Lead the development of full chip and/or chiplet level STA convergence from early stages to signoff.
- Collaborate with top-level floor plan and clock planning teams to ensure seamless integration.
- Optimize CAD signoff flows and methodologies to drive convergence and efficiency.
- Integrate digital partitions' and analog IPs' timing, providing feedback to PD/RTL and driving convergence.
- Work closely with logic design and DFT engineers to define and implement constraints for various work modes, including runtime and efficiency optimization.
Requirements:
- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
- 3-8 years of experience in physical design and STA.
- Proven experience in RTL2GDS and STA design and convergence.
- Familiarity with physical design EDA tools, such as Synopsys and Cadence.
- Hands-on STA experience from early stages to signoff using Synopsis Primetime, with deep knowledge in timing concepts.
- Excellent teamwork and communication skills.
NVIDIA is a company that values innovation, creativity, and collaboration. If you're a motivated and autonomous engineer who thrives in a fast-paced environment, we encourage you to apply for this exciting opportunity to join our team of industry leaders.
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