Senior ASIC Design Manager
1 day ago
As a Senior ASIC Design Manager at Mulya Technologies, you will play a pivotal role in shaping the design and development of complex ASICs and System-on-Chip architectures for various electronic devices.
Key Responsibilities- Collaborate with architecture and physical design teams to create power/area/performance optimized RTL designs.
- Participate in block and chip-level verification processes.
- Rigorously run Lint, CDC/RDC, and LEC checks to ensure high-quality designs.
- Develop and implement block and chip-level constraints, and execute synthesis.
- Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, accompanied by 8-12 years of industry experience.
- Proficiency in hardware description languages (Verilog, VHDL) and microarchitecture modeling tools (SystemVerilog, SystemC).
- Familiarity with SoC design methodologies, including RTL design, synthesis, timing analysis.
- Able to self-verify RTL blocks/top level before handing off to the DV team.
- Exposure to Analog digital interfaces and physical layer development for standards like Ethernet, USB3, MIPI is highly preferred.
- Exposure to STA, DFT, and physical design is highly preferred.
- Excellent communication and teamwork skills, with a strong ability to work independently as a highly motivated individual contributor.
$120,000 - $180,000 per annum, depending on location and qualifications.
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