Senior ASIC Design and STA Engineer
2 weeks ago
NVIDIA is seeking a highly skilled ASIC STA Engineer to join our Networking Silicon engineering team, where you will be responsible for developing high-speed communication devices that deliver exceptional performance and efficiency. As a key member of our team, you will have the opportunity to design and develop groundbreaking large-scale chips that drive innovation in the industry.
Key Responsibilities:
- Converge full chip and/or chiplet level STA from early stages to signoff.
- Participate in top-level floor plan and clock planning.
- Optimize CAD signoff flows and methodologies.
- Integrate digital partitions' and analog IPs' timing, providing feedback to PD/RTL and driving convergence.
- Collaborate with logic design and DFT engineers to define and implement constraints for various work modes, including optimization for runtime and efficiency.
Requirements:
- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
- 3-8 years of experience in physical design and STA.
- Proven experience in RTL2GDS and STA design and convergence.
- Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
- Hands-on STA experience from early stages to signoff using Synopsis Primetime, with deep knowledge in timing concepts.
- Excellent teamwork and communication skills.
NVIDIA is a technology-focused company that values innovation and collaboration. If you are a creative and autonomous engineer who thrives in a fast-paced environment, we encourage you to apply for this exciting opportunity to join our team of experts in physical design.
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