
Senior Technical Lead
7 days ago
The primary objective of this role is to lead the design verification team in ensuring that our products meet the required specifications and quality standards.
- Key Responsibilities:
- Understand business requirements and functional specifications of IPs, subsystems, and SOC
- Develop and maintain verification environment architecture documents
- Review and revise code to meet acceptance criteria
- Develop code in System Verilog, UVM, C, and VHDL for unit, subsystem, and SOC level verification
- Perform RTL simulations using Synopsys and Cadence simulators
- Debug and resolve problems found by simulations
- Develop performance test plans and maintenance
- Implement transactors, monitors, and models for performance verification
- Provide full reports of performance metrics and bottlenecks
- Track tickets and code releases using Bug Tracking tool and GIT
- Perform UPF-based Power Aware simulations
- Coding of Assertion and Functional Coverage bins in SVA
- Code and Functional Coverage Closure
- Preparing and conducting reviews of Verification Sign-off documents to ensure SOC tape-out quality
7+ years of experience in design verification
Strong understanding of System Verilog, UVM, and VHDL
Excellent problem-solving skills and attention to detail
Ability to work in a fast-paced environment and prioritize tasks effectively
Experience with Synopsys and Cadence simulators
Knowledge of power aware simulations and assertion-based verification
Strong communication and teamwork skills
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