ACL Digital | Design Verification Engineer

Hi, Greetings from ACL Digital, Looking for Lead Design Verification Engineers Exp Level:7+ Years Location : Bangalore JD: 7+ Years of experience in Design verification Must have Expertise: 1. Grounds up verification environment development using SV/ UVM is a must 2. One of the high speed protocols like PCIe or USB 3 or MIPI 3. Experience...

Hi,Greetings from ACL Digital,Looking for STA/ Synthesis Engineer: 1. Exp: 3+ years2. Availability: immediate to 30 days3. Experience in Synthesis, STA, Lint, CDC, Spyglass, Formal Verification and good debugging skills.4. CLP/LEC.Interested can share CV to sharmila.b@acldigital.com

Hi, Greetings from ACL Digital, Looking for STA/ Synthesis Engineer: 1. Exp: 3+ years 2. Availability: immediate to 30 days 3. Experience in Synthesis, STA, Lint, CDC, Spyglass, Formal Verification and good debugging skills. 4. CLP/LEC. Interested can share CV to

Talented and motivated Mid-Level CPU Subsystem Design and Verification Engineer to join our growing team. Responsibilities: Design:Participate in the design of CPU subsystems, collaborating with architects and design engineers.Contribute to micro-architectural decisions, considering performance, power, and area trade-offs.Develop detailed design documents...

Hi, Greetings from ACL Digital, Looking for Lead Design Verification Engineers Exp Level:7+ Years Location : Bangalore JD: 7+ Years of experience in Design verification Must have Expertise: 1. Grounds up verification environment development using SV/ UVM is a must 2. One of the high speed protocols like PCIe or USB 3 or MIPI 3. Experience...

JD:This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies. Key Responsibilities:Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies.Design and implement verification environments using SystemVerilog and UVM methodologies.Develop test cases to validate...

Talented and motivated Mid-Level CPU Subsystem Design and Verification Engineer to join our growing team. Responsibilities : Design : Participate in the design of CPU subsystems, collaborating with architects and design engineers. Contribute to micro-architectural decisions, considering performance, power, and area trade-offs. Develop detailed design...

ResponsibilitiesCollaborate with designers, architects, and verification teams to verify the design, architecture, and micro-architecture of ASICs. This includes developing the verification infrastructure, defining the verification scope, and using advanced verification methodologies. SkillsUse computer hardware languages like Verilog, and have experience...

ACL Digital is hiring for PD and STA Engineers for Bangalore and Location. 3+years of experience in Physical Design. Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure. Notice period- Immediate to 30 days

Hello Semicons#ACL Digital looking for "Memory Design Engineers"Interested share your CV to sharmila.b@acldigital.comExp Level:2+ yearsLocation: BangaloreNotice Period: Immediate joiners are prefferedDuration: Full Time Job DescriptionInvolved in design of all types of memory compiler like SRAM, registerfiles, ROM generators. memory design / circuit design...

Hi, Greetings from ACL Digital We are looking for "DFT Engineers" Exp Level: 5+ Description: We are seeking an experienced DFT Engineer with industry experience in the VLSI domain to join our dynamic team. The ideal candidate will have a strong background in Design for Testability (DFT) methodologies and techniques, with a proven track record of...

Hello All, Greetings from ACL Digital, We are looking for "Emulation Engineers" Experience Level: 6 to 10years Location :Bangalore Job Description: Worked on bringing up SOC/Subsystem/IP emulation model using Zebu/Veloce/Paladium. Specially worked on Graphics IPs, ARM subsystem, X86 cores, PCIE, USB. Has good RTL design understanding. Good to have: Has...

ACL Digital is looking for an Experienced Layout Engineer Minumum 4+ years of Experience for Bangalore LocationGood to have ESD BlocksMust have Lower nodes from TSMC AMS/IO Memory - Layout Interested share/refer karthick.v@acldigital.comBachelor's or Master's Degree with 4 - 12 years of Analog Layout experienceDemonstrated leadership experience of at least 3...

Principal RTL Design Engineer & Architect Bangalore We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in leading state of the RTL designs involving solutions for automotive camera and display systems. Responsibilities • Design and develop microarchitectures...

Job Location: Bangalore/ Hyderabad/Pune and NoidaNotice Period: 15 days to 30 DaysMinimum: 4 YearsKey Responsibilities:Developing test plansCoding and bring up of asm, c++ testsUVM test bench components coding and maintainingDebugging regression failsProtocol: DDR,PCIE,USB,MIPIPreferred Experience:Should have worked on Processor based System or Sub-system...

JD: This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies. Key Responsibilities: Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies. Design and implement verification environments using SystemVerilog and UVM methodologies. Develop test cases to validate...

JD: This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies. Key Responsibilities: Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies. Design and implement verification environments using System Verilog and UVM methodologies. Develop test cases...

JD: This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies. Key Responsibilities: Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies. Design and implement verification environments using SystemVerilog and UVM methodologies. Develop test cases...

• Bachelor's degree in Science, Engineering, or related field.• 7+ years ASIC design, verification, or related work experience.• At least 5 years of experience with the ISO 26262 / IEC 61508 standard including hands-on experience with Failure Modes and Effect Analysis (FMEA), Fault Tree Analysis (FTA) and Failure Modes Effect and Diagnostic Analysis...

• Bachelor's degree in Science, Engineering, or related field. • 7+ years ASIC design, verification, or related work experience. • At least 5 years of experience with the ISO 26262 / IEC 61508 standard including hands-on experience with Failure Modes and Effect Analysis (FMEA), Fault Tree Analysis (FTA) and Failure Modes Effect and Diagnostic Analysis...