SOC DFT Engineer

SoC DFT Engineer Job Description: Scan insertion. SCAN DRC/Coverage debug. ATPG Pattern generation. Gate level simulations ( Zero delay/Timing Delay simulations). Worked on JTAG/P1500 protocols. Perl/Tcl scripting. Timing/Formal verification/PD flow knowledge is plus. Location: Bangalore Notice Period: Immediate Experience: 5+...

L&T Technology is hiring for Senior DFT Engineers / Lead DFT Engineer with 8-15 Years of experience. Job Location : Bangalore Skills Expertise should be : ATPG, SOC, ASIC DFT.

Job Title: Lead DFT EngineerExperience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC DesignJob Summary:We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with...

Job Title: DFT EngineerExperience Level: 4+ yearsLocation: Hyderabad/BanglaoreJob Description:Key Responsibilities:Develop and implement DFT architecture and methodologies for ASIC/SoC designs.Insert and verify scan chains (scan insertion, ATPG, scan stitching).Implement MBIST/Logic BIST using industry-standard tools and flows.Work on boundary scan (IEEE...

Job Description- The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these. The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts. Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and...

Experience : 4+years Location : Bangalore Job Description Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes implementation...

Experience: 4+yearsLocation: BangaloreJob DescriptionWill be responsible for Designing and Implementing DFT techniques.Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.Test Modes implementation and verification, scan...

DFT Engineer Experience : 3 years Location : Bangalore Develop and implement DFT architecture for ASIC/SoC designs. Insert and verify scan chains, boundary scan (JTAG), MBIST, LBIST, and other test structures. Collaborate with RTL and physical design teams to ensure seamless integration of DFT features. Generate and validate test patterns...

Key skills with hand on: DFT, MBIST, Scan Insertion, ATPG, Full Chip ,SOC ,VLSI Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil) Detailed JD: 5+ years' experience in ASIC/DFT - simulation and Silicon validation, •Should have worked in at least one...

Key skills with hand on: DFT, MBIST, Scan Insertion, ATPG, Full Chip ,SOC ,VLSIExperience: 5 - 25 yearsWork Location: Trivandrum, Bangalore, Hyderabad, Chennai, PuneEducation: Engineering (excluding Mechanical/Civil)Detailed JD:5+ years' experience in ASIC/DFT - simulation and Silicon validation, •Should have worked in at least one Full chip DFT...