Modernize Chip Solutions

Minimum 15+ Years of experience SoC Physical Design.Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm.Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must.This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...

Minimum 15+ Years of experience SoC Physical Design. Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...

Minimum 15+ Years of experience SoC Physical Design. Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...

About the Company - Modernize Chip solutions About the Role - PD - Director Responsibilities - Minimum 15+ Years of experience So C Physical Design. Have working experience in advanced Fin FET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys Pn R/STA tools and Calibre; good scripting/automation skills is a must. Work hands-on...

Experience: 5+ years Location: Bangalore Back end STA with skills on Innovas 3, 5, 7 nm, Prime time Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....) Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis) Will need to be hands-on, defining...

Experience: 5+ yearsLocation: BangaloreBack end STA with skills on Innovas 3, 5, 7 nm, Prime time Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis)Will need to be hands-on, defining...

About the Company - Modernize Chip solutions About the Role -Analog Layout Location - Hyderabad/Bangalore

About the Company - Modernize Chip solutionsAbout the Role -Analog LayoutLocation - Hyderabad/Bangalore

About the Company - Modernize Chip solutionsAbout the Role - PD - DirectorResponsibilities -Minimum 15+ Years of experience SoC Physical Design.Have working experience in advanced FinFET node designs 7nm/5nm/3nm.Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must.Work hands-on to solve critical design and...

Experience: 8+ years Location: Bangalore Back end STA with skills on Innovus 3, 5, 7 nm, Prime time

Experience: 8+ yearsLocation: BangaloreBack end STA with skills on Innovus3, 5, 7 nm, Prime time

About the Company - Modernize Chip solutions About the Role -Analog Layout Location - Hyderabad/Bangalore

About the Company - Modernize Chip solutionsAbout the Role -Analog LayoutLocation - Hyderabad/Bangalore

About the Company - Modernize Chip Solutions offers VLSI design, software, and IT services for next generation products. We deliver end-to-end solutions of the best quality with the shortest development cycle to the global semiconductor industry. Responsibilities - 4 to 8yrs Qualifications - B.Tech/ B.E (EC) or M.Tech/ME (VLSI Design). - Required Skills -...

Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity...

Description:Role and Responsibilities• Minimum of 6 to 8 years of hands-on physical design implementation experience along with APR flow development and STA analysis.• Through knowledge in PD flow setup and STA Flows.• process technology nodes (16 nm and above) preferred.• Through knowledge and hands-on experience with Low Power Implementation and...

Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues.Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity...

Responsibilities: Develop and execute verification plans for complex digital RTL. Utilize the latest verification tools and methodologies, including UVM (Universal Verification Methodology), System Verilog, and formal verification techniques. Create and maintain testbenches, test cases, and verification environments. Create and automate regression flow....

Position Description: Design and develop RTL in Central Engineering team for products which includes blocks such as wakeup sequencing, calibration logic, I3C/I2C protocol, interrupt controller, EEPROM, MCU integration etc Convert Architecture specification to Micro-architecture specification, implement logic functions in RTL using Verilog/System Verilog...

Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity...