Principal Design Engineer(Physical Design)
3 months ago
Position Description:
Exp: 7-12 Yrs
· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
· The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.
· Working closely with RTL design team & Analog Team to ensure successful tapeouts.
· Responsibility includes participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes
Position Requirements:
· B.Tech/BE/ME/Mtech with hands-on experience in physical design and verification.
· Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understanding deep sub-micron technology issues.
· Solid knowledge of LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, and DFM.
· Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus.
· Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl.
-
Principal design engineer(physical design)
4 weeks ago
Pune, India Cadence Design Systems Full timePosition Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have the opportunity to work on many varieties of...
-
Principal Design Engineer(Physical Design)
6 months ago
Pune, India Cadence Design Systems Full timePosition Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...
-
Principal design engineer(physical design)
4 weeks ago
Pune, India Cadence Design Systems Full timePosition Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...
-
Principal Design Engineer(Physical Design)
4 weeks ago
pune, India Cadence Design Systems Full timePosition Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...
-
Principal Design Engineer(Physical Design)
6 months ago
pune, India Cadence Design Systems Full timePosition Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...
-
Principal Design Engineer(Physical Design)
6 months ago
Pune, India Cadence Design Systems Full timePosition Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...
-
Principal Design Engineer(Physical Design)
6 months ago
Pune, India Cadence Design Systems Full timePosition Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have the opportunity to work on many varieties of...
-
Principal Design Engineer(Physical Design)
6 months ago
Pune, India Cadence Design Systems Full timePosition Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...
-
pune, India Cadence Design Systems Full timePosition Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...
-
pune, India Cadence Design Systems Full timePosition Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have the opportunity to work on many varieties of...
-
Principal Design Engineer
6 months ago
Pune, India Cadence Design Systems, Inc. Full timeDescription Exp- 8- 12 Yrs Education: BE/ B Tech/ ME/ M Tech / MS B.Tech/BE/ME/Mtech with hands-on experience physical design , timing closure and physical verification. Exp with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues. Solid knowledge on physical design flow, Timing...
-
Senior Physical Design Lead
3 weeks ago
Pune, Maharashtra, India Cadence Design Systems, Inc. Full timeCadence Design Systems, Inc.Estimated Salary: $150,000 - $200,000 per yearAbout UsWe are a leading technology company that provides electronic design automation (EDA) software and services to help our customers create complex integrated circuits.Job DescriptionWe are seeking an experienced Senior Physical Design Lead to join our team. As a key member of our...
-
Principal Physical Design
6 months ago
Pune, India Ampere Full timeDescription The Role We are looking for an experienced Physical Design / CAD Engineer, Principal level, to join our small but growing Processor Design group, advancing the art of high performance implementation and physical design. Ideal candidates will develop and maintain physical design flows for high performance designs. What You'll Do: ...
-
Design Engineer
3 months ago
pune, India Cadence Design Systems Full timePosition Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have the opportunity to work on many varieties of...
-
Principal Design Engineer
5 months ago
Pune, India Lattice Semiconductor Full timeOverview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales,...
-
Senior Principal Software Engineer
1 month ago
Pune, Maharashtra, India Cadence Design Systems Full timeThe Cadence Advantage :Collaborative InnovationWe're seeking a talented Senior Principal Software Engineer to join our team at Cadence Design Systems. This is an exceptional opportunity to work on cutting-edge technology and make a meaningful impact.Our CultureCadence's unique 'One Cadence - One Team' culture promotes collaboration and teamwork, ensuring...
-
Physical Design Engineer
5 months ago
Pune, India Lattice Semiconductor Full timeOverview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales,...
-
Cadence Design Systems
3 months ago
Pune, India Cadence Design Systems Full timeThe Cadence Advantage :- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.- Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in...
-
Cadence Design Systems
2 weeks ago
Pune, India Cadence Design Systems Full timeThe Cadence Advantage : - The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.- Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in...
-
Senior ASIC Physical Design Engineer
2 weeks ago
Pune, Maharashtra, India Lattice Semiconductor Full timeJob SummaryWe are seeking a highly skilled Senior ASIC Physical Design Engineer to join our team at Lattice Semiconductor in Pune, India. The successful candidate will be responsible for driving physical design closure of key ASIC blocks and full chip, developing best-in-class methodologies to achieve best power, performance, and area.The ideal candidate...