Soc Implementation Specialist

4 days ago


bangalore, India beBeeOptimization Full time

Job Position: Physical Design EngineerWe are seeking a highly skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for the RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure.This is a unique opportunity for an experienced designer to contribute their expertise in RTL-to-GDSII implementation, floorplanning, placement, routing, and physical verification to our dynamic team.The successful candidate will own block-level or full-chip implementation from RTL to GDSII, ensuring seamless integration with other teams.Key responsibilities include performing floorplanning and placement, clock tree synthesis (CTS), routing and optimization, run and close timing (STA), IR drop, EM, DRC, LVS, and antenna checks across various corners and scenarios.The chosen candidate will drive physical verification and signoff processes, collaborating closely with RTL, DFT, STA, and power teams for successful project execution.Ongoing tasks will involve implementing and debugging low-power design techniques using UPF/CPF-based flows, as well as applying congestion analysis, ECOs, and timing fixes across critical paths.The ideal candidate will leverage their expertise to optimize SoC blocks for performance, power, and area using EDA tools and foundry guidelines, preparing detailed design reports and supporting tapeout activities throughout the project lifecycle.



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