High-Speed Analog Layout Expert Wanted

2 weeks ago

bangalore, India beBeeAnalog Full time

Job Title: Senior Analog Layout EngineerAre you a highly skilled and experienced analog layout engineer looking for a new challenge? Do you have a passion for designing high-speed analog IPs and working closely with cross-functional teams to deliver robust layout quality and performance?We are seeking a Senior Analog Layout Engineer to join our team, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision. As an individual contributor, you will operate independently, leveraging your deep technical expertise in chip-level integration, hierarchy, and physical interfaces.Key Responsibilities:Handle chip-level planning and integration of high-speed analog IPsPerform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimizationRun post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematicStrong understanding of ICC2 flows for complete SoC/top-level integrationLead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checksDrive complete IP signoff ownership, ensuring zero violations at final GDS deliveryWork closely with foundry teams for clarifications on PDKs, LVS/DRC rule updates, model issues, PEX rule discussions, tape-out requirements, and signoff guidelinesCoordinate with PD, DV, circuit design, and packaging teams for smooth IP-level deliveryPrepare and deliver IP documentation, abstracts, verification reports, and GDSMandatory experience in TSMC 5NM technologyRequired Skills and Qualifications:8+ years of solid experience in Analog/Mixed-Signal LayoutDeep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks)Strong understanding of chip-level integration, hierarchy, and physical interfacesHands-on experience with ICC2 and top-level integration flowsAbility to run simulations for the blocks being designed (post-layout, extracted)Very detailed understanding of IP-level verification, DRC/LVS/ERC, PEX/RC extraction, signoff decks, and reliability checksProven experience interacting with foundry teams for rule clarifications and IP/tape-out signoffExcellent command of Cadence Virtuoso, PVS, Calibre, and extraction toolsStrong ownership of IP delivery, customer communication, and documentationGood to Have: Experience with advanced nodes (5nm), exposure to SERDES / PCIe / MIPI / USB high-speed IPs, and experience working with global customersBenefits and Compensation:As a member of our team, you can expect a competitive compensation package and excellent benefits, including remote work opportunities, flexible hours, and career growth opportunities. We offer a dynamic and supportive work environment that fosters innovation, collaboration, and professional development.Equal Opportunity Statement:We are committed to diversity and inclusivity, providing equal opportunities to all qualified candidates regardless of their background, race, gender, age, or disability. We encourage applications from diverse candidates who share our values and are passionate about contributing to our team's success.Location: Remote/India (must support USA/Canada time zone)Travel: Willing to travel to the U.S. for project release (as required)],

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