Senior Cache and Memory Design Engineer-Barcelona

RTL Engineers Description We have multiple open positions in our RTL team and we're looking for individuals with either a strong RTL or a strong architecture/microarchitecture background interested in working in several areas of a RISC-V design for an advanced technology node. In particular, areas of focus will be the processor pipeline, d-cache, i-cache,...

Senior Verification Engineer Description We are hiring! Are you passionate about microprocessor architecture ? We need you! As a Senior Verification Engineer , you will work within the Verification Team and play a crucial role in ensuring the correctness and functionality of complex digital designs at the Register Transfer Level according to the...

𝗟𝗲𝗮𝗱 𝗠𝗲𝗺𝗼𝗿𝘆 𝗗𝗲𝘀𝗶𝗴𝗻 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗥𝗲𝘀𝗽𝗼𝗻𝘀𝗶𝗯𝗶𝗹𝗶𝘁𝗶𝗲𝘀: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. 𝗥𝗲𝗾𝘂𝗶𝗿𝗲𝗱...

The ideal candidate will be responsible for executing and leading the full design process from ideation to production.During the creation process, you will ensure that our designs meeting all necessary design responsibilities. Qualifications Bachelor's Degree or equivalent experience in Engineering or relevant technical degree Minimum 2 years of job...

Job Title: Memory Layout Engineer Experience: 3+yrs Location: Bangalore Job Type: Full-time Industry: Semiconductors / VLSI / Memory Design Job Summary: We are looking for a Memory Layout Engineer with strong expertise in physical layout design of memory components such as SRAM, ROM, Register Files, or custom memory IPs. The candidate will...

Job Description: 3-8 years of experience in Memory/Custom Layout design. Location: Bangalore Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet...

This is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing,...

ACL Digital is looking for smart and enterprising Memory Layout Engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting. Experience: 4 to 5 Years Skills : Having lower node Finfet experience. (10nm & less) Memory compiler layout, SRAM, Register File (RF)...

SoC Design Lead – HBM & LPDDR Memory Controllers Bangalore / Hyderabad Job Title: SoC Design Lead – HBM & LPDDR Memory Controllers We are a well-funded early-stage startup building the next generation of high-performance SoC design technologies. We’re seeking a seasoned SoC Design Lead with expertise in memory controller microarchitecture and RTL...

Exp: 3 to 8 Years Location: Bangalore Notice: Immediate - 15 days ✅ Memory Leafcell layout library design from scratch including top level integration. ✅ Good knowledge on different types of memory architectures. ✅ Good knowledge in optimized layout design for better performance. ✅ Sound knowledge & hands on experience in Finfet technology, layout...