Senior RTL Design Engineer-Barcelona

Cache and memory EngineerDescription Are you passionate about microprocessor architecture? We need you! As a Senior Cache and Memory Design Engineer, you play a crucial role in designing and developing memory subsystem solutions for our semiconductor portfolio. You will work within the Cache and Memory Design Team and work closely with other teams’...

Senior Verification Engineer Description We are hiring! Are you passionate about microprocessor architecture ? We need you! As a Senior Verification Engineer , you will work within the Verification Team and play a crucial role in ensuring the correctness and functionality of complex digital designs at the Register Transfer Level according to the...

RTL Design Engineer for Interface Controller IP development team. Position is based in Bangalore or Noida. The role would include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence. The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as...

Position: RTL Design Engineer Experience: 5 - 8 Years Qualifications: BE/Btech in ECE/EEE Responsibilities - The candidate should have strong RTL design experience. Strong design experience in Ethernet IPs or Ethernet protocol domain. Knowledge in Verilog/VHDL languages Scripting languages: TCL/Perl/Python (any one). Knowledge of AXI Protocols.

Hi All, Greetings' from Eximietas Design....! We are Hiring ASIC SOC RTL Design Engineer/Leads. Job Title: ASIC SOC RTL Design Engineer/Leads ..! Experience: 8+ Years. Location: Bengaluru. Job Description: Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you...

College education in Electronics Engineering or Computer Engineering Exp- 7-15 Yrs - Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. - Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. - Functional...

Hi All, Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic...

Hi All, Eximietas Hiring Senior Physical Design Leads/Architects/Managers/Sr. Managers Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. . About the job Qualification Required: Typically requires a minimum of 10+ years of experience in Physical Design with mainstream...

Hi All, Eximietas Hiring Senior Physical Design Leads/Architects/Managers/Sr. Managers Experience: Min 8+ Years. Location: Visakhapatnam. About the job Qualification Required: Typically requires a minimum of 8+ years of experience in Physical Design with mainstream P&R tools Bachelors OR Masters Degree Engineering in Electronics or Electrical or...

Hi All, Eximietas Hiring Senior Physical Design Leads/Managers. Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. About the job Qualification Required: Typically requires a minimum of 10+ years of experience in Physical Design with mainstream P&R tools ...