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Senior DFT Engineer
2 months ago
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
JR49511 Senior DFT EngineerMicron is awarded as a Great Place to Work in India We focus on innovation through Integrity and inclusion. We are proud to have a set of core values(People, Innovation, Tenacity, Collaboration and Customer Focus) which is reflected in our culture Micron is a diverse organization of dedicated and innovative individuals, and we provide equal opportunities to all. At Micron, we don't discriminate on the basis of race, color, religion, gender, sexual orientation, disability, identity, national origin, or status as a protected veteran.
As a Micron's ASIC DFT team we implement DFT for Micron IPs and Memory controllers(SOC) developed for different type of Storage products in Micron. We are using the best in class DFT methodologies and process technologies to ensure that we deliver the best quality products to achieve the lowest DPPM numbers.
We work closely with Design(RTL), DV, Physical Implementation team, Test Engineering and Product Engineering team to support early analysis to the Silicon bring-up and Characterization.
Required Skills and Experience :
Bachelor’s or Master’s Degree or equivalent experience in Electronics Engineering, Microelectronics, Software Engineering or a related field. The role of Senior DFT engineer require 5+ years of industry experience with shown ability in DFT of highly sophisticated SOCs :
Core skills include Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG ( & IEEE1687), Fault Simulation, ATPG Fault models(SAF, TDF, SDD, PDT etc), SDF annotated gate level verification, Scan and Memory Diagnosis. Must have experience with Siemens, Synopsys and/or Cadence Cad tools. Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python.Responsibilities -
Accountable for innovative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level. Generate and validate ATPG patterns using simulations. Shall Validate the DFT implementation using RTL and Gate level simulation. Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation. Support the Silicon bring up activities to guarantee the highest stability of the test patterns/program. Chip in to the overall DFT methodology development.Nice to have Skills/Experience :-
Shall have Knowledge of IEEE , 1500 and 1838. Good experience on Hierarchical Scan implementations with core wrapping concepts Experience in handling multi-clock domains and low power design implementation. Knowledge/Experience on SSN, or 3D IC DFT implementation. Communicate effusively with multi-functional functional teams in different geographies and time Zones. Time management and multi-tasking skills.
Job Location:
You will be joining part of growing team in Hyderabad or Bangalore. We value People and our dedication is to reward people with multiple Micron benefits that include PTO and medical benefits to name the few.
