Memory Controller

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore (WFH ) A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. Memory Controller - Principal / Senior Staff Verification Engineers: looking for...

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore (WFH ) A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. Memory Controller - Principal / Senior Staff Verification Engineers: looking for...

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore (WFH )A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. Memory Controller - Principal / Senior Staff Verification Engineers: looking for experienced...

Memory Layout Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning...

Job Description: Memory Layout Engineer Experience - 2+ years We are seeking a highly skilled and experienced Memory Layout Engineer to join our team. The ideal candidate will have hands-on expertise in designing and integrating layouts for advanced memory blocks across leading-edge process technologies. You will play a critical role in developing...

Senior Memory PHY architect Location: Bangalore We enable tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking,...

JD for DDR Memory validation engineer:Education: BE in Electronic and communicationsExperience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs)Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance.This is a Work from...

Job Description: Memory Layout EngineerExperience - 2+ yearsWe are seeking a highly skilled and experienced Memory Layout Engineer to join our team. The ideal candidate will have hands-on expertise in designing and integrating layouts for advanced memory blocks across leading-edge process technologies. You will play a critical role in developing and...

Location : Bangalore, IndiaExperience : 3-7 Years Notice Period : Immediate or up to 1 Month About the Role :We are seeking an experienced Firmware Engineer specializing in either Security or Memory Firmware to join our Research & Development (R&D) team. The role involves managing the complete software life cycle, including analysis, development,...

Senior Memory PHY architectLocation: Bangalore We enable tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking,...

Senior Memory PHY architect Location: Bangalore We enable tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking,...

Memory LayoutHands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning...

JD for DDR Memory validation engineer:Education: BE in Electronic and communicationsExperience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs)Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance.This is a Work from...

JD for DDR Memory validation engineer: Education: BE in Electronic and communications Experience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs) Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance. This is a Work from...

JD for DDR Memory validation engineer:Education: BE in Electronic and communicationsExperience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs)Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance.This is a Work from...

JD for DDR Memory validation engineer: Education: BE in Electronic and communications Experience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs) Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance. This is a Work from...

Job Description:Good understanding of basic VLSI concepts: CMOS, IC Fabrication, FINFET, RC Network etc.Experience with developing tight pitched memory (SRAM & MRAM etc) array layout with hierarchy layouts of Row decoders, Write drivers, Assist circuits, Sense Amplifiers, Memory Control circuitCollaborate with circuit designers to meet design specifications...

Role: Layout Design of SRAM/CAM/RF custom/compiler memories in 5FF/3FF technologies.Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Knowledge of EM/IR requirements. level integration, final verification of...

Role: Layout Design of SRAM/CAM/RF custom/compiler memories in 5FF/3FF technologies. Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Knowledge of EM/IR requirements. level integration, final...

Applied Materials, Inc. is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the...