Senior Analog Layout Professional

3 days ago

guntur, India beBeeAnalog Full time

Senior Analog Layout EngineerWe are seeking a highly experienced professional to lead our team in the development of high-speed analog IPs. The ideal candidate will have strong expertise in chip-level handling, deep understanding of ICC2-based top-level integration, and the ability to independently run block-level simulations.This role requires full ownership of IP development, verification, integration, and delivery. The engineer will work closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.Handle chip-level planning and integration of high-speed analog IPs.Perform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimization.Run post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematic.Strong understanding of ICC2 flows for complete SoC/top-level integration.Lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks.Drive complete IP signoff ownership, ensuring zero violations at final GDS delivery.Required Skills and Qualifications:8+ years of solid experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks).Strong understanding of chip-level integration, hierarchy, and physical interfaces.Hands-on experience with ICC2 and top-level integration flows.Ability to run simulations for the blocks being designed (post-layout, extracted).Very detailed understanding of: o IP-level verification o DRC/LVS/ERC o PEX/RC extraction o Signoff decks & reliability checks.The ideal candidate will have excellent command of Cadence Virtuoso, PVS, Calibre, and extraction tools, as well as strong ownership of IP delivery, customer communication, and documentation.Benefits:Excellent salary and compensation package.Remote work option with flexibility to travel to the U.S. for project release (as required).

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