High-Speed Analog Layout Specialist

5 days ago

bikaner, India beBeeSeniorAnalogLayoutEngineer Full time

Job DescriptionWe are seeking a highly experienced Senior Analog Layout Engineer with strong expertise in chip-level handling of high-speed analog IPs, deep understanding of ICC2-based top-level integration, and the ability to independently run block-level simulations.The ideal candidate must have very strong IP verification knowledge and experience coordinating with foundry teams for signoff, tape-out, and model-related interactions. This role requires full ownership of IP development, verification, integration, and delivery.This is a remote position that involves working closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance. The engineer will handle chip-level planning and integration of high-speed analog IPs, perform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimization.The successful candidate will be responsible for running post-layout simulations (extracted netlist, corners, Monte Carlo) and ensuring correlation with schematic. A strong understanding of ICC2 flows for complete SoC/top-level integration is also required.In addition, the engineer will lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks. They will drive complete IP signoff ownership, ensuring zero violations at final GDS delivery.Key Responsibilities: Handle chip-level planning and integration of high-speed analog IPs Perform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimization. Run post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematic. Strong understanding of ICC2 flows for complete SoC/top-level integration. Lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks. Drive complete IP signoff ownership, ensuring zero violations at final GDS delivery.Required Skills and QualificationsThe ideal candidate should have the following skills and qualifications:Experience: 8+ years of solid experience in Analog/Mixed-Signal Layout.Deep Expertise: High-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks).Understanding: Chip-level integration, hierarchy, and physical interfaces.Flows: ICC2 and top-level integration.Simulations: Ability to run simulations for the blocks being designed (post-layout, extracted).Verification: Very detailed understanding of IP-level verification, DRC/LVS/ERC, PEX/RC extraction, signoff decks & reliability checks.Tools: Excellent command of Cadence Virtuoso, PVS, Calibre, and extraction tools.Interactions: Proven experience interacting with foundry teams for rule clarifications and IP/tape-out signoff.BenefitsThis role offers a competitive salary and benefits package, as well as opportunities for professional growth and development. If you are a motivated and experienced Senior Analog Layout Engineer looking for a new challenge, we encourage you to apply.OthersPlease note that this is a remote position that requires the ability to work effectively in a team environment. We are committed to diversity and inclusivity in our hiring practices.

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