Physical Verification Engineer

Physical Verification Engineer Job Description Work with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...

Physical Verification EngineerJob DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.Co-work with Place & Route team to resolve full-chip layout integration issues.Work with various implementation team to drive Physical VerificationCoordinates...

Experience of 5+ years in Physical verification and closure. Location: Bangalore NP - Immediate Main responsibility of the candidate will be around achieving a clean GDS view with below key items: Physical Verification closure for Arm CPU implementation: Should have completed multiple tape-outs with Physical Verification closure role in the past Strong...

Experience of 5+ years in Physical verification and closure. Location: BangaloreNP - ImmediateMain responsibility of the candidate will be around achieving a clean GDS view with below key items:Physical Verification closure for Arm CPU implementation:Should have completed multiple tape-outs with Physical Verification closure role in the pastStrong...

Job Summary We are seeking a highly experienced Senior Physical Design Engineer with a minimum of 10 years in the RTL to GDSII flow. This role requires hands-on expertise with Cadence Innovus , experience at N3 and below process nodes , and strong scripting and flow debugging skills . Key Responsibilities Lead physical design activities from RTL to GDSII,...

Responsibilities: Complete ownership of Physical Design activities from Floorplan to GDS including PnR,STA,Physical Verification, Take complete ownership for implementation of both Top/Block level designs. Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree...

Technical Requirements Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team. In-depth knowledge of floor planning, power planning, PNR and signoff checks Strong experience in static timing analysis (STA), timing closure, and signal integrity. Expertise in power...

Experience: 3 - 6 Years Notice period: Immediate Location: Bangalore & Hyderabad Responsibilities Mandatory Experience in Full Chip Timing . Strong background in digital IC design , including floorplanning, placement, routing, clock tree synthesis, and optimization. Tools Expertise : Proficient in Innovus , ICC2 , and Fusion Compiler for place and route,...

About Company At 7Rays Semiconductors ( , we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies We work closely with our...

Job Summary We are seeking a highly experienced Senior Physical Design Engineer with a minimum of 10 years in the RTL to GDSII flow. This role requires hands-on expertise with Cadence Innovus , experience at N3 and below process nodes , and strong scripting and flow debugging skills . Key Responsibilities Lead physical design activities from RTL to GDSII,...