Design Verification Engineer

1 week ago

bangalore, India Sintegra Inc. Full time

We are seeking a skilled and motivated Design Verification Engineer (DV) with expertise in Ethernet protocols, MAC layer functionality, and RoCE (RDMA over Converged Ethernet). The ideal candidate will have hands-on experience with Synopsys Ethernet PHY and controller IPs, and a strong understanding of high-performance networking technologies.Key ResponsibilitiesDevelop and execute verification plans for Ethernet MAC and PHY IP blocksDesign and implement testbenches using industry-standard methodologies (UVM, SystemVerilog)Validate RoCE protocol implementations for low-latency, high-throughput data transferCollaborate with design and architecture teams to ensure functional correctness and performanceDebug and resolve issues across simulation and emulation platformsContribute to coverage analysis and closurePreferred QualificationsStrong knowledge of Ethernet protocols, including MAC layer operationsExperience with RoCE (RDMA over Converged Ethernet) and its application in high-speed networkingFamiliarity with Synopsys Ethernet PHY and controller IPsProficiency in SystemVerilog, UVM, and simulation tools (VCS, Questa, etc.)Background in ASIC/FPGA design and verificationExcellent problem-solving and communication skillsBonus SkillsExposure to high-performance computing or data center architecturesExperience with formal verification or emulation platformsKnowledge of PCIe, TCP/IP stack, or other networking protocols

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