DV- PCIE Verification Engineer

Exciting Opportunities in Taras System and Solutions Designation: Lead Engineer (DV) Experience: 10+ years Notice Period: Immediate to 30 days Roles and Responsibilities: JD for DV engineers (10-15 years of experience) - SOC Verification Experience on ARM Ecosystem Test cases Experience in C and C++ - PCIE Experience and also PCIE-VIP usage experience - GLS...

Exciting Opportunities in Taras System and SolutionsDesignation: Lead Engineer (DV)Experience: 10+ yearsNotice Period: Immediate to 30 daysRoles and Responsibilities:JD for DV engineers (10-15 years of experience)- SOC Verification Experience on ARM EcosystemTest cases Experience in C and C++- PCIE Experience and also PCIE-VIP usage experience- GLS working...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience.Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verificationDevelop functional tests based on verification test planDrive Design...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologiesExperience in development of UVM based...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, India Detailed JD is as below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience.Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verificationDevelop functional tests based on verification test planDrive Design...

Job Location: Bangalore/ Hyderabad Notice Period: 15 days to 30 Days Minimum: 4 Years Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: DDR,PCIE,USB,MIPI, PCIE Preferred Experience: Should have worked on Processor based System or...

Job Location: Bangalore/ Hyderabad Notice Period: 15 days to 30 Days Minimum: 4 Years Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: DDR,PCIE,USB,MIPI, PCIE Preferred Experience: Should have worked on Processor based System or...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

Design Verification ExpertWe are seeking a highly skilled and experienced verification expert to join our team. The ideal candidate will have a strong background in verification methodologies, System Verilog programming skills, excellent problem-solving skills, and the ability to work collaboratively in a fast-paced environment.The job involves developing...