Static Timing Analysis Engineer

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same. Job Description Key Responsibilities: 1. Timing Analysis & Closure - Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. - Achieve timing closure by resolving violations and optimizing paths. 2. Constraint Development - Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths). - Integrate constraints from multiple IPs for hierarchical STA. 3. Tool Usage & Flow Integration - Use STA tools like Synopsys PrimeTime, Cadence Tempus, or equivalent. 4. Integrate STA into the overall design flow and automate processes for efficiency. - Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, and multi-cycle paths for Full Chip, Sub-system and complex IP timing closure. - Define and implement timing constraints from scratch such as clock definitions, input/output delays, and path constraints for Full-Chip, Sub-system to ensure accurate timing analysis. - Able to integrate the existing timing constraints from various IP for Full-Chip/Sub-system timing analysis. - Deep knowledge of STA tools (such as Synopsys PrimeTime, Cadence Tempus, or Mentor Graphics' ModelSim) including their capabilities, limitations, and best practices. - Guide the integration of STA tools into the overall design flow, ensuring compatibility and optimal performance. - Oversee the process of achieving timing closure, addressing any timing violations and guiding optimizations to meet performance goals. Primary Skills: - Deep Technical Knowledge: - In-depth understanding of STA concepts, EDA tools, and methodologies. - Experience in timing constraints development, timing closure for Full-Chip/Sub-system to meet the design performance. - Problem-Solving Skills: Strong analytical and problem-solving abilities to tackle complex timing issues. - Communication Skills: Ability to communicate complex technical concepts effectively to various stakeholders. - Leadership and Mentoring: Experience in leading teams and mentoring less experienced engineers in STA practice Secondary skills: - Design flow management - Able to improve the execution efficiency through flow automation and other value adds - Cross functional co-ordination - Work closely with other teams, such as RTL design, Physical design, design, verification, and manufacturing, to ensure seamless timing closure of physical design. E Educational Qualifications: Bachelor’s or Master’s Degree in:Electrical Engineering/Electronics & Communication Engineering/VLSI Design/Computer Engineering or related fields Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fuelled by its market leading capabilities in AI, cloud and data, combined with its deep industry expertise and partner ecosystem. The Group reported 2023 global revenues of €22.5 billion.