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Verification Lead
4 weeks ago
Requirement 1: Verification Lead/Engineer
Experience: 4+ years (Lead: 10+ years)
Key Skills:
- RTL verification of SDIO, UART, SPI, WDT, GPT, eUSB and other low-speed peripherals
- Strong in SystemVerilog, UVM, Assertions & Coverage
- Experience with VCS, Questa, Xcelium
- Power-aware simulation using UPF, Gate-Level Simulation (GLS)
- Functional coverage closure & regression debug
- Exposure to AXI/APB, I2C protocols a plus
Requirement 2: GLS DV Engineer
Experience: 3–8 years (Lead: 5+ years)
Key Skills:
- Gate-Level Simulation hands-on (Unit delay, SDF)
- Power-aware GLS (UPF/CPF) integration
- GLS integration into RTL DV flows
- Debug timing and power intent at IP/Sub-system/SoC level
- Strong in Verilog/SystemVerilog, scripting (Python, TCL)
- Tools: VCS, Xcelium, Questa
Send resume to: prabhu.p@acldigital.com
WhatsApp: +91 8754387484
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