
Physical Design Engineer
20 hours ago
Should be able to handle Full chip hashtag
Added advantage for #Innovus with Minimum 4 years
#PnR (timing/congestion/CTS issues), understanding of hashtag
#IO ring,
#package support, multi hashtag
#voltage design.
🔸Deep understanding of the concepts related to hashtag
#synthesis, place & route, hashtag
#CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure.
🔸Responsible for independent planning and execution of all aspects of physical design including /
#floor_planning,
#place_and_route,
#Clock_Tree_Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, hashtag
#Physical_Verification,
#DFM.
🔸Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification,
#IREM).
🔸Well versed with the timing closure (#STA), timing closure methodologies
Good Understanding of DRC, LVS,
#ERC and PERC rule files for lower tech node layout verification.
🔸Experience in
#lower tech
#node (
🔸Good automation skills in hashtag
#PERL,
#TCL and EDA tool-specific scripting.
🔸Able to take complete ownership for Block/sub-system for complete execution cycle.
𝗤𝘂𝗮𝗹𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻
🔸BE/BTECH/MTECH in EE/ECE with proven experience in hashtag#ASIC Physical Design.
🔸Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired
𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 4+ Years
𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻: 𝗕𝗮𝗻𝗴𝗮𝗹𝗼𝗿𝗲.
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