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Design Engineering Group Director
4 weeks ago
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Director of Engineering : Design Verification
We offer amazing opportunities to grow, no matter where you are in your career.
Job Description
Roles & Responsibilities:
- Management of a Die-to-Die SerDes PHY groups DV and Modeling group focusing on MDV verification including: Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, development of models, overseeing AMS verification including but not limited to CoSim, and mentorship of junior engineers.
- Planning the execution of multiple projects that run concurrently and close collaboration with PMs and other domain leads and management to enable efficient execution with high quality
- The ability to work with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions.
- Customer interactions including pre and post-sales activities: DV methodology review and customer support.
- Participate in Technical alignment with verification experts in defining verification strategy, architecting verification environment.
- Represent DV and technically work/lead team interactions with RTL, analog/modeling, PD teams, PM and management for design verification tasks.
- Lead the effort to define, develop and deploy new functional verification methodologies, ensuring unified methodology across different projects that are executed by the group.
Skillsets
- The candidate should have a strong background in functional verification fundamentals, verification environment planning & development, test plan creation.
- The candidate should have experience in planning execution, leadership and management.
- Prior digital verification experience in some of the serial bus multiprotocol PHY IPs is expected, experience in D2D communication IP such as UCIe is preferred.
- The candidate should have a good understanding of RTL/design and be able to work closely and collaborate with RTL team.
- Other verification domain skills:
- Strong expertise in Verilog, HVL( SV, e) with UVM/OVM/eRM methodology
- Experience in assertions development/closure, constraint randomization, functional coverage, code coverage
- Strong RTL and GLS sim debug skills
- Expertise in more than two of following skills is desirable and added plus:
- Power-aware RTL set-up, simulation and debug
- Formal verification
- Gate-level timing/no-timing simulations
- Some experience or understanding of Analog modelling. Mixed-mode simulations with Analog/digital ( AMS)
- Some exposure to Automotive IP verification (fault injection), emulation exposure though not mandatory but good to have
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