RTL Design Engineer
5 days ago
Job Description RTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 Years Job Description Job Role: - Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. - Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. - Integrate complex subsystems into SoC environments and support design convergence. - Collaborate with system architects, verification, SoC, software, DFT, and physical design teams. - Apply low-power design techniques including clock gating, power gating, and multi-voltage domains. - Analyze and optimize for performance, area, and power. - Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. - Conduct CDC and lint checks using tools like Spyglass and resolve waivers. - Participate in post-silicon debug and bring-up activities. Job Qualification - 13 years of experience in digital front-end ASIC/RTL design. - Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. - Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable. - Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. - Experience with wireless modem IPs or similar high-performance digital blocks is a plus. - Familiarity with low-power design methodologies and CDC handling. - Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. - Exposure to post-silicon debug and SoC integration challenges. - Strong documentation and communication skills. - Self-motivated with a collaborative mindset and ability to work with minimal supervision. About Company ACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. Partner with us to turn complexity into clarity and shape the future of your organization.
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RTL Design Engineer
3 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:- Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.- Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.- Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer
3 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 Years Job Description Job Role: - Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. - Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. - Integrate complex subsystems into SoC environments and support...
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RTL Design Engineer
2 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 Years Job Description Job Role: Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer
2 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:- Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.- Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.- Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer
3 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer
1 day ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer-CXL
2 weeks ago
india Tata Consultancy Services Full timeRTL Design Engineer(CXL) Experience - 5+yrs Location- BangaloreJD Strong RTL designer with IP design experience SoC Integration Interconnect Generation for a given configuration CXL 3.1 and above design experience
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Lead RTL Design Engineer
3 days ago
Chennai, India ACL Digital Full timeLead RTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 6 to 9 YearsJob Description6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.Experience with RTL coding using Verilog/VHDL/System...
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Lead RTL Design Engineer
2 days ago
Chennai, India ACL Digital Full timeLead RTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 6 to 9 YearsJob Description6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.Experience with RTL coding using Verilog/VHDL/System...
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Lead RTL Design Engineer
1 day ago
Chennai, India ACL Digital Full timeLead RTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 6 to 9 YearsJob Description6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.Experience with RTL coding using Verilog/VHDL/System...
