Lead RTL Design Engineer
3 days ago
Lead RTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 6 to 9 YearsJob Description6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.Experience with RTL coding using Verilog/VHDL/System Verilog.Experience in micro-architecture & designing cores and ASICs.Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc.Exposure in scripting (Pearl/Python/TCL).Strong debugging capabilities at Synthesis, timing analysis & implementationCollaborate closely with cross-function team to research, design and implement performance, constraints and power management strategy for product roadmap.Good team player. Need to interact with the other teams/verification engineers proactively.Ability to debug and solve issues independently.About CompanyACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack — from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. Partner with us to turn complexity into clarity and shape the future of your organization.
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Lead RTL Design Engineer
2 days ago
Chennai, India ACL Digital Full timeLead RTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 6 to 9 YearsJob Description6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.Experience with RTL coding using Verilog/VHDL/System...
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Lead RTL Design Engineer
1 day ago
Chennai, India ACL Digital Full timeLead RTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 6 to 9 YearsJob Description6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.Experience with RTL coding using Verilog/VHDL/System...
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Lead RTL Design Engineer
3 days ago
Chennai, India ACL Digital Full timeLead RTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 6 to 9 YearsJob Description6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.- Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.- Experience with RTL coding using Verilog/VHDL/System...
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Lead RTL Design Engineer
3 days ago
Chennai, India ACL Digital Full timeLead RTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 6 to 9 Years Job Description 6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable. - Strong Domain Knowledge on RTL Design, implementation, and Timing analysis. - Experience with RTL coding using Verilog/VHDL/System...
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RTL Design Engineer
3 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:- Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.- Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.- Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer
3 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 Years Job Description Job Role: - Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. - Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. - Integrate complex subsystems into SoC environments and support...
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RTL Design Engineer
2 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 Years Job Description Job Role: Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer
2 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:- Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.- Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.- Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer
3 days ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer
1 day ago
Chennai, India ACL Digital Full timeRTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.Integrate complex subsystems into SoC environments and support design...
