RTL Design Engineer-CXL

RTL Design Engineer(CXL)Experience - 5+yrsLocation- BangaloreJDStrong RTL designer with IP design experienceSoC IntegrationInterconnect Generation for a given configurationCXL 3.1 and above design experience

Job DescriptionPosition Description:- RTL Design Engineer forInterface ControllerIP developmentteam.- Position is based inBangaloreor Noida.- The role is for PCIe Architect with ARM CPU subsystem architecture, including memory subsystem design, IO and cache subsystems.- The role would also include design and support of the RTL of the PCIe/CXL/IDE/UALink IP...

Job DescriptionJob DetailsJob Description:- Part of the global PCIe/CXL Center of Excellent (CoE) team, developing the latest & state of the art PCIe/CXL solution for next generation FPGA in the latest process technology node.- Develops logic/RTL design and simulation for IP/SoC design & integrates logic of IP blocks and subsystems into a full chip SoC or...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.Exp= 8- 14yrsRTL Design using Verilog is a must.System...

Hi All,Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point...

Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating...

Hi All,Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Hi All, Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Hi All,Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...