RTL Design Engineer-CXL

RTL Design Engineer(CXL) Experience - 5+yrs Location- Bangalore JD Strong RTL designer with IP design experience SoC Integration Interconnect Generation for a given configuration CXL 3.1 and above design experience

RTL Design Engineer(CXL)Experience - 5+yrsLocation- BangaloreJDStrong RTL designer with IP design experienceSoC IntegrationInterconnect Generation for a given configurationCXL 3.1 and above design experience

RTL Design Engineer for Interface Controller IP development team. Position is based in Bangalore or Noida. The role would include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence. The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean...

Job Overview: We are seeking an experienced RTL Design Engineer to join our team. The successful candidate will be responsible for designing and supporting the RTL of PCIe/CXL/IDE/UALink IP solution.">">The ideal candidate will have a strong background in digital design, with experience in Verilog and SystemVerilog. Additionally, they should have a good...

Design Verification Expert for PCIe and CXLAbout the Job: We're seeking an experienced Design Verification Engineer to join our innovative team. This role involves comprehensive verification of PCIe and/or CXL IP and Subsystem, utilizing System Verilog and UVM methodology.Key Responsibilities:Develop and implement verification plans for PCIe and/or CXL IP...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.Exp= 8- 14yrsRTL Design using Verilog is a must.System...

Hi All,Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Hi All, Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Hi All,Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Hi All,Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...