
Sr Principal Design Engineer
2 days ago
- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
- Exp= 8- 14yrs
- RTL Design using Verilog is a must.
- System Verilog experience and experience with UVM based environment usage / debugging is required.
- PCIe experience is a must.
CXL/PXC experience desired.
We're doing work that matters. Help us solve what others can't.-
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