GLS DV Engineer

Exciting Opportunities in Taras System and Solutions Designation: Lead Engineer (DV) Experience: 10+ years Notice Period: Immediate to 30 days Roles and Responsibilities: JD for DV engineers (10-15 years of experience) - SOC Verification Experience on ARM Ecosystem Test cases Experience in C and C++ - PCIE Experience and also PCIE-VIP usage experience - GLS...

Exciting Opportunities in Taras System and SolutionsDesignation: Lead Engineer (DV)Experience: 10+ yearsNotice Period: Immediate to 30 daysRoles and Responsibilities:JD for DV engineers (10-15 years of experience)- SOC Verification Experience on ARM EcosystemTest cases Experience in C and C++- PCIE Experience and also PCIE-VIP usage experience- GLS working...

Job Title: GLS DV EngineerWe are seeking an experienced DV engineer to join our team in Bengaluru. As a key member of our engineering team, you will be responsible for developing and integrating GLS designs with RTL environments.Key Responsibilities:TB flow development for GLS, integrate with RTL DV environmentCreation of GLS databaseUnit delay, power-aware,...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience.Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verificationDevelop functional tests based on verification test planDrive Design...

Job Description- Pre Silicon DV of Peripheral SDIO, UART, SPI, QSPI, WDT, GPT, eUSB and could be other low speed peripherals- Test plan development, Test development, RTL verification- Regression, coverage, use case closure- Support power and performance tests development for same peripherals- GLS and timing simulation of the same

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, India Detailed JD is as below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience.Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verificationDevelop functional tests based on verification test planDrive Design...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologiesExperience in development of UVM based...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

Hiring Now – Immediate Joiners Only | Location: Bangalore (Onsite) Requirement 1: Verification Lead/EngineerExperience : 4+ years (Lead: 10+ years)Key Skills :RTL verification of SDIO, UART, SPI, WDT, GPT, eUSB and other low-speed peripheralsStrong in SystemVerilog, UVM , Assertions & CoverageExperience with VCS, Questa, XceliumPower-aware simulation...