Dft

3 weeks ago

Bengaluru Karnataka, India Sarvajith Infotech Full time

Hi All,

Now we are looking for DFT Role.

Experience:

- 15 to 20yrs

Sakary:

- 35L

Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full chip level
- Should have good knowledge about all DFT concepts Scan insertion and validation, BIST, LBIST, MBIST insertion and validation, ATPG and Pattern Validation w/wo Timing, DFT mode timing Analysis and sign off.
- Understanding of DFT architectures like Boundary scan (JTAG), Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification.
- Must have experience generating scan patterns and coverage statistics for various fault models like stuck at (Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories (E-fuse etc.).
- **Experience in Coverage Analysis.**
- Synopsys tools**:DFT MAX, TetraMAX, VCS** Cadence tools**:Genus, Modus, Xcelium. **Mentor Graphics tools: T**essent tool chain, TestKompress.**
- Should be responsible for the cross functional issues and dependencies across RTL integration, synthesis, constraints, timing analysis and related analysis and debugs
- Familiar to Verilog and RTL simulation
- Good Knowledge on Spyglass.
- Experience with gate level pattern simulations and debug
- Exposure to post silicon debug is a plus
- Scripting skills: Perl, TCL

**Expectations from the Role**
- Excellent debugging and problem-solving skills
- Effective communication skills to interact with all stakeholders
- Must be highly focused and remain committed to obtaining closure on project goals.
- Ability to work independently and complete work assigned
- Should possess good Leadership Skills
- Should have a Go-getter attitude

Schedule:

- Day shift

**Experience**:

- total work: 10 years (preferred)

Work Location: In person

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