Dft Eng

We're looking for outstanding talent to help deliver mind-blowing Ethernet products. If you want your fingerprints all over technologies for hyperscale cloud service and telecommunications data centers then we want to hear from you. NCCG is a team helping pave the way for an iconic Silicon Valley technology company to transform from a PC company to one that powers the cloud and billions of smart, connected computing devices. We are an R and D powerhouse in the Network and Edge Group, one of Intel's growth engines. Help accelerate our growth by joining our team of problem solvers, experimenters, and innovators dedicated to designing advanced Ethernet network technologies that are transforming data center ecosystems. Your day will be anything but ordinary. Some of the things you'll do: - Code, document, design, and release according to latest industry-proven DFT processes - Create a DFT environment that is open, modular, scalable, well documented, and with fully integrated diagnostics. Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block. Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

**Qualifications**:

- Driving scan solutions for large SOCs, focusing on last-mile coverage and first-time-right silicon patterns. EDA vendor-supported scan architectures and tools covering synthesis, timing, DRC, ATPG, GLS, and tester bring-up. Technically hands-on in creating and deploying solutions. Influencing and collaborating with multiple teams across Intel

**Inside this Business Group**:
The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

**Posting Statement**:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Benefits**:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

**Working Model**:
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. **In certain circumstances the work model may change to accommodate business needs.**
JobType

Hybrid