Phy Regression Testing-bangalore

About the RoleWe are seeking a highly skilled Senior Verification Engineer to join our team in Tech Mahindra. As a key member of our verification team, you will be responsible for designing and implementing verification environments for HSIO PHY integration.Key Responsibilities:Design and develop verification environments for HSIO PHY integration at...

About the Role">We are seeking a highly skilled LPDDR5/LPDDR4 expert to lead our validation efforts at Tech Mahindra. As a Senior DDR PHY Verification Engineer, you will be responsible for delivering high-quality test plans and vectors to ensure the successful validation of our designs.">Key Responsibilities">">Develop and execute comprehensive test plans to...

Job Title: Senior Quality Assurance EngineerJob Summary:We are seeking a highly skilled Senior Quality Assurance Engineer to join our team at LAERDAL BANGALORE LLP. The successful candidate will be responsible for ensuring the highest quality of our software products by designing and executing comprehensive test plans, identifying defects, and collaborating...

Responsibilities :- Working extensively in test design, test case creation, test automation, execution, and feature end-to-end testing.- Development and maintenance of automation frameworks (web and API), test scripts using Java or Python.- Identifying gaps and providing inputs to improve the quality of the process and product.- Coordinating with...

Job Responsibilities:HSIO PHY Integration and So C levelHSIO PHY IP level test case porting to So C levelHSIO PHY So C level Test case development, Running regression in RTL/GLS & Timing simulationsHSIO PHY Virtual tester simulations in RTL/GLS & Timing simulationsHands-on experience in System Verilog, OVM/UVM based constrained random...

Job Responsibilities:HSIO PHY Integration verification @ Sub-system and SoC levelHSIO PHY IP level test case porting to SoC levelHSIO PHY SoC level Test case development, Running regression in RTL/GLS & Timing simulationsHSIO PHY Virtual tester simulations in RTL/GLS & Timing simulationsHands-on experience in System Verilog, OVM/UVM based constrained random...

Client of ConnectproExp-6+yrs expTo be part of a highly skilled and challenging high speed parallel # PHYsuch as # DDR, #LPDDRetc design team.Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etcResponsible for various aspects of...

Job Responsibilities: HSIO PHY Integration verification @ Sub-system and SoC level HSIO PHY IP level test case porting to SoC level HSIO PHY SoC level Test case development, Running regression in RTL/GLS & Timing simulations HSIO PHY Virtual tester simulations in RTL/GLS & Timing simulations Hands-on experience in System Verilog, OVM/UVM based constrained...

Job Responsibilities: HSIO PHY Integration verification @ Sub-system and SoC level HSIO PHY IP level test case porting to SoC level HSIO PHY SoC level Test case development, Running regression in RTL/GLS & Timing simulations HSIO PHY Virtual tester simulations in RTL/GLS & Timing simulations Hands-on experience in System Verilog, OVM/UVM based constrained...

Job Responsibilities: HSIO PHY Integration verification @ Sub-system and SoC level HSIO PHY IP level test case porting to SoC level HSIO PHY SoC level Test case development, Running regression in RTL/GLS & Timing simulations HSIO PHY Virtual tester simulations in RTL/GLS & Timing simulations Hands-on experience in System Verilog, OVM/UVM based...

Client of ConnectproExp-6+yrs expTo be part of a highly skilled and challenging high speed parallel # PHY such as # DDR, #LPDDR etc design team.Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etcResponsible for various aspects of...

Client of ConnectproExp-6+yrs expTo be part of a highly skilled and challenging high speed parallel # PHY such as # DDR, #LPDDR etc design team.Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etcResponsible for various aspects of...

About the Role:We are seeking an experienced Senior Physical Verification Engineer to join our team at Tech Mahindra.Job Summary:The successful candidate will be responsible for verifying HSIO PHY integration at the sub-system and SoC level, as well as developing test cases and simulations for HSIO PHY IP level testing.Main Responsibilities:

Client of ConnectproExp-6+yrs expTo be part of a highly skilled and challenging high speed parallel #PHY such as #DDR, #LPDDR etc design team.Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etcResponsible for various aspects of...

Client of Connectpro Exp-6+yrs exp To be part of a highly skilled and challenging high speed parallel #PHY such as #DDR, #LPDDR etc design team. Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etc Responsible for various aspects...

Client of ConnectproExp-6+yrs expTo be part of a highly skilled and challenging high speed parallel #PHY such as #DDR, #LPDDR etc design team.Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etcResponsible for various aspects of...

Design Verification EngineerExperience. 5+ YearsNP- Immediate- 30 daysExperience on either IP level verification (protocol verification) or SOC-level verification· Proficiency in Verilog, System Verilog, VHDL, C, System C, SV-UVM· Understanding of code coverage, functional coverage, assertions, cover groups etc· Protocols : PCIe, CXL, Ethernet, (High...

Design Verification EngineerExperience. 5+ YearsNP- Immediate- 30 daysExperience on either IP level verification (protocol verification) or SOC-level verification· Proficiency in Verilog, System Verilog, VHDL, C, System C, SV-UVM· Understanding of code coverage, functional coverage, assertions, cover groups etc· Protocols : PCIe, CXL, Ethernet, (High...

Design Verification EngineerExperience. 5+ YearsNP- Immediate- 30 daysExperience on either IP level verification (protocol verification) or SOC-level verification· Proficiency in Verilog, System Verilog, VHDL, C, System C, SV-UVM· Understanding of code coverage, functional coverage, assertions, cover groups etc· Protocols : PCIe, CXL, Ethernet, (High...

Design Verification EngineerExperience. 5+ YearsNP- Immediate- 30 daysExperience on either IP level verification (protocol verification) or SOC-level verification· Proficiency in Verilog, System Verilog, VHDL, C, System C, SV-UVM· Understanding of code coverage, functional coverage, assertions, cover groups etc· Protocols : PCIe, CXL, Ethernet, (High...