Design Verification Engineer
1 month ago
Project Description:
Join our team in developing cutting-edge technology. This role demands a high level of expertise in Testing. The ideal candidate has a background in SW engineering, data structures, verification processes, with
strong fundamentals in scripting language and Verilog. The candidate should have a fair understanding
of SW quality and processes.
Responsibilities:
The candidate will be responsible for design, development and
maintenance, of clients device model verification tools. We are looking for smart, creative people who have a passion for solving challenging problems.
Mandatory Skills:
Candidate should have 2-4 years' experience
Strong Familiarity with System Verilog and OVM/UVM Verification Methodology
Knowledge of system-level architecture including buses like AXI/AHB/APB/ACE5
Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim
Ability to work with cross-functional teams
Proficiency in developing the TB environment
Good Knowledge on writing coverage and assertions
Good knowledge in scripting(Perl/Tcl/Python) and automation of verification flows/process
Knowledge of mipi, video Ips like ISP/Encoder/Decoder would be useful
Nice-to-Have Skills:
Education : B.Tech/M.Tech ECE
Languages:
English: B2 Upper Intermediate
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