ASIC Engineer/Lead
2 weeks ago
Role : ASIC Engineer/Lead, Design :
- Define and implement IP/SoC verification plans, build Verification test benches to enable IP/sub-system/SoC level verification.
- Develop functional tests based on Verification test plan.
- Drive Design Verification to closure based on defined Verification metrics on test plan, functional and code coverage.
- Debug, root-cause and resolve functional failures in the Design, partnering with the Design team.
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon Validation teams towards ensuring the highest Design quality.
Qualifications :
- 5+ years of hands-on experience in System Verilog/UVM methodology and/or C/C++ based Verification.
- Experience in Cadence EDA tools such as Xcelium, Jasper Formal Verification Platform and Scripting (Python, TCL, Perl, Shell) used to build tools and flows for Verification environments.
- Experience in Architecting and Implementing Design Verification Infrastructure and executing the full Verification cycle.
- Experience with Design Verification of Data-centre applications like Video, AI/ML and Networking Design.
- Experience in one or more of the following areas along with functional Verification - SV Assertions, Formal, property-based, Emulation.
- Track record of 'first-pass success' in ASIC development cycles
- Knowledge of Agile/iterative development processes.
- Hands on experience in leading the Verification based Design and Development solutions
- Proficiency in Agile/Scrum methodology.
- Starting experience in leading the small teams and handling the Customer calls
- Experience on API based System Integration is an added advantage.
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