ASIC Design Engineer
2 months ago
About Infinera
Infinera is one of the world's leading providers of carrier-class optical networking products and services worldwide. Our solutions carry data over subsea optical cables, between cities and data centres. Infinera is building the next generation of pluggable optical modules and compact open modular optical systems.
Infinera India Pvt. Ltd, Bangalore, is the largest Engineering group within Infinera with a team of 400+ people and is a critical execution team since the past 15 years.
Infinera India ASIC team provides ASIC and FPGA solutions for all client facing interfaces in Infinera's systems. A dedicated team of 70 ASIC engineers gets to own and work on the Architecture, Design, Verification of Next Generation client interface solutions.
As a company, Infinera has a culture and history of challenging conventional engineering thinking.
The ASIC team takes pride in its engineering acumen, its teamwork, and the difference it makes to the quality and timeliness of our ASIC solutions.
We are looking to add passionate, highly motivated, and talented Engineers to our mix of seasoned Engineers and fresh college graduates. Verification, emulation, platform experts who develop SW and FW
Infinera provides the Network Connectivity Solutions for the World’s most demanding Networks. As an Infinera employee, you will be solving the industry’s toughest problems by leading, not following. Collaborate across our diverse culture, global reach and reap its benefits.
ASIC team is responsible for providing in house ASIC/FPGA solutions that are at the core of the Infinera Networking Solutions.
Role:
In this role you are expected to work with architects to understand the requirements, document them and implement the functional block or an IP.
What the peron will be doing:
• Work closely with Architects to understand the requirements, document them, and implement the functional block or an IP
• Capture the design intent, uArch, RTL coding, API coding, lint, constraints development, CDC, and synthesis
• Debug the designs and work with verification team members to get a functionally clean block
• Integrate blocks and create physical design blocks for place and route
• Work with Physical Design team to ensure that the design meets area, timing, power requirements
• Test their design block in the lab and work with lab validation team members
What we seek:
• Ability to abstract complex functions
• Ability to do the uArch using block diagrams, waveforms and mathematical and logical models/equations
• Good understanding of use of FIFOs, state machines
• Exposure to RTL coding using Verilog/system Verilog
• Good logic design skills with ability to understand timing, area and power reports
• Experience in timing constraints development, running lint and CDC checks, synthesis using ASIC or FPGA tools
• Interested in using assertions and formal property verification to develop bug free designs
• Experience of 5+ years in design (uArch, RTL coding, RTL checks and debug)
- Preferred: Prior experience in Ethernet/Networking domain
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