Senior dv engineer
4 weeks ago
LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, India Detailed JD is as below :: Job Description DV Positions: Define and implement IP/So C verification plans, build verification test benches to enable IP/sub-stem/So C level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 5 + of hands-on experience in Stem Verilog/UVM methodology and/or C/C++ based verification 5+ experience in IP/sub-stem and/or So C level verification based on Stem Verilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience with verification of ARM/RISC-V based CPU sub-stems or So Cs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control stems like Mercurial(Hg), Git or SVN
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Dv engineer
3 weeks ago
Bangalore, India Modernize Chip Solutions Full timeRole: Design Verification Engineer Skill: DV with GLS Exp NP: Immediate to 30 days Loc: HYD Exp: 3+ yrs Role: Design Verification Engineer Skill: DV-IP with Ethernet/PCIE NP: Immediate to 30 days Loc: HYD Exp: 10+ yrs Role: Design Verification Engineer Skill: DV with Soc, GLS Exp NP: Immediate to 30 days Loc: HYD Exp: 3+ yrs Role: Design...
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Dv engineer
4 weeks ago
Bangalore, India Modernize Chip Solutions Full timeRole: Design Verification Engineer Skill: DV with GLS Exp NP: Immediate to 30 days Loc: HYD Exp: 3+ yrs Role: Design Verification Engineer Skill: DV-IP with Etehrent/PCIE NP: Immediate to 30 days Loc: HYD Exp: 10+ yrs
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Dv engineer
2 weeks ago
Bangalore, India Modernize Chip Solutions Full timeRole: Design Verification Engineer Skill: DV with GLS Exp NP: Immediate to 30 days Loc: HYD Exp: 3+ yrs Role: Design Verification Engineer Skill: DV with Soc, Arm Processor NP: Immediate to 30 days Loc: BLR Exp: 6+ yrs
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Dv engineer
1 week ago
Bangalore, India Modernize Chip Solutions Full timeRole: Design Verification Engineer Skill: DV with GLS Exp NP: Immediate to 30 days Loc: HYD Exp: 3+ yrs Role: Design Verification Engineer Skill: DV with Soc, Arm Processor NP: Immediate to 30 days Loc: BLR Exp: 6+ yrs
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Senior DV Engineer
2 weeks ago
bangalore, India L&T Technology Services Full timeLTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design...
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Senior DV Engineer
2 weeks ago
bangalore, India L&T Technology Services Full timeLTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, India Detailed JD is as below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive...
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Senior DV Engineers
1 week ago
bangalore, India L&T Technology Services Full timeLTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...
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Senior DV Engineers
2 weeks ago
bangalore, India L&T Technology Services Full timeLTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...
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Dv practice head
4 weeks ago
Bangalore, India Evoke HR Solutions Pvt. Ltd. Full timeDesignation- DV – Practice Head Key Responsibilities Lead and scale the Design Verification (DV) practice by building high-performing teams and driving technical excellence. Define and implement advanced verification strategies, methodologies, and best practices for complex So C, FPGA, and ASIC projects. Collaborate with architecture, design, and...
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Senior Design Verification Engineer
1 day ago
bangalore, India HCLTech Full timeStrictly Not accepting applications below 7 years.Design Verification Engineer (Senior Level - 7+ years’ experience)Company: HCL TechJob Summary:We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a...
