Dv engineer

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, India Detailed JD is as below :: Job Description DV Positions: Define and implement IP/So C verification plans, build verification test benches to enable IP/sub-stem/So C level verification Develop functional tests based on verification test plan ...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design...

Designation- DV – Practice Head Key Responsibilities Lead and scale the Design Verification (DV) practice by building high-performing teams and driving technical excellence. Define and implement advanced verification strategies, methodologies, and best practices for complex So C, FPGA, and ASIC projects. Collaborate with architecture, design, and...

Staff DV Methodology EngineerWe are a US based Stealth mode Start-uplocation: Hyderabad / Bangalore / Remote ( any where in India )We unify the processes used in Semiconductor and Hardware Systems design - thus reducing bugs, improving efficiency and productivityOur breakthrough technology has drawn investment from Silicon Valley’s boldest VCs and...

Designation- DV – Practice Head Key Responsibilities Lead and scale the Design Verification (DV) practice by building high-performing teams and driving technical excellence. Define and implement advanced verification strategies, methodologies, and best practices for complex SoC, FPGA, and ASIC projects. Collaborate with architecture, design, and...

Designation- DV – Practice HeadKey ResponsibilitiesLead and scale the Design Verification (DV) practice by building high-performing teams and driving technical excellence.Define and implement advanced verification strategies, methodologies, and best practices for complex SoC, FPGA, and ASIC projects.Collaborate with architecture, design, and product teams...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

Staff Gen AI DV Methodology Engineer We are a US based Stealth mode Start-up location: Hyderabad / Bangalore / Remote ( any where in India ) We unify the processes used in Semiconductor and Hardware Systems design - thus reducing bugs, improving efficiency and productivity Our breakthrough technology has drawn investment from Silicon Valley’s boldest...

Staff Gen AI DV Methodology EngineerWe are a US based Stealth mode Start-uplocation: Hyderabad / Bangalore / Remote ( any where in India )We unify the processes used in Semiconductor and Hardware Systems design - thus reducing bugs, improving efficiency and productivityOur breakthrough technology has drawn investment from Silicon Valley’s boldest VCs and...

Who are we and what do we do? The HVP team in TI develops power solutions for a wide array of end-equipments, with several hundreds of volts of withstand capability. This team in TI offers one of the world's largest comprehensive portfolios of high-performance AC/DC and isolated DC/DC controllers, Ga N-integrated power-stages and converters, and modules...