Senior Verification Manager
1 week ago
Senior Manager, ASIC Verification
Position Description
To be part of a highly skilled and challenging high speed PHY and IO buffer design team working on the newest technology nodes (12nm and below).Responsible for overall ASIC, IP and sub-system verification from test plan creation, UVM development to signoff.Manager a team of talented Design Verification engineersEnsure first pass product through multi-dimensional verification coverage including mixed mode verification.Leading, mentoring and coaching team membersPair with similar domain specialists across other geographical locations on core technical initiativesWork closely with Digital and Analog designersEqual opportunity position with excellent pay package
SKILLS Required
Strong knowledge of ONFI, DDR/LPDDR JEDEC and DFI protocolsExposure to verification of complex high speed PHY and/or complex AMS IPsProven track record of building testplan, UVM environment and testbenches for ONFI, DDR and IO buffer IP and ASICsExperience with RTL debugging, score boarding and code coverage analysisSound knowledge of Verilog and System Verilog languagesExposure to modelling and validating complex analog circuits in Verilog and Verilog-AExperience of complex mixed signal design verification using state of the art flows and toolsThe position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.Team leadership experience, including planning and managing tasks is requiredM.S./M.Tech, BS/BE (Electronics)
Experience Required : 14+ Years
Contact:UdayMulya
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