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Senior Verification Manager
6 days ago
Senior Manager, ASIC Verification
Top10 Semiconductor Organization in the world
Hyderabad
Senior Manager, ASIC Verification
Position Description
- To be part of a highly skilled and challenging high speed PHY and IO buffer design team working on the newest technology nodes (12nm and below).
- Responsible for overall ASIC, IP and sub-system verification from test plan creation, UVM development to signoff.
- Manager a team of talented Design Verification engineers
- Ensure first pass product through multi-dimensional verification coverage including mixed mode verification.
- Leading, mentoring and coaching team members
- Pair with similar domain specialists across other geographical locations on core technical initiatives
- Work closely with Digital and Analog designers
- Equal opportunity position with excellent pay package
SKILLS Required
- Strong knowledge of ONFI, DDR/LPDDR JEDEC and DFI protocols
- Exposure to verification of complex high speed PHY and/or complex AMS IPs
- Proven track record of building testplan, UVM environment and testbenches for ONFI, DDR and IO buffer IP and ASICs
- Experience with RTL debugging, score boarding and code coverage analysis
- Sound knowledge of Verilog and System Verilog languages
- Exposure to modelling and validating complex analog circuits in Verilog and Verilog-A
- Experience of complex mixed signal design verification using state of the art flows and tools
- The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
- Team leadership experience, including planning and managing tasks is required
- M.S./M.Tech, BS/BE (Electronics)
Experience Required : 14+ Years
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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