STA Application Engineer

Senior STA EngineerResponsibilities:§ Hands on responsibility in top level timing constraints generation/debug on complex GPU/SOCs including configuring different timing modes (Func, DFT, JTAG, MBIST, etc).§ Work with a team of engineers on timing closure and constraints generation/debug.§ Has prior STA & timing closure experience.§ Understanding of...

Hello All,We are seeking a skilled and experienced STA Engineer to join our team. ,Job Description- Deep understating and experience of STA tool Tempus/PrimeTime /Tweaker/ DMSA(PTECO) .- Knowledge of timing corners/modes, process variations and signal integrity related issues are required.- Experience in timing closure of high frequency blocks & subsystems...

Mirafra Technologies Hiring STA - PTPX Engineers:1. STA PTPX - Team / Senior / Lead2 .Hands on : Timing closure, STA, Primetime, PTPX.3. Experience : 5 - 8 years4. Location - Bangalore5. NP - 0 to 30 daysSkills - Primetime, Timing closure, Prime power analysis, Power extraction, power estimation, Verdi/ FSDB, PTPXWe are however looking for shorter notice...

Hi,I am excited to announce that #Tessolve is hiring for Experienced #STA Engineers to join our dynamic team in #Bangalore!Expertise in handling timing closure of complex GPU designs, DDR designs with advancedtechnology nodes like 5nm 4nm.● Expertise in Block level Timing Analysis and timing convergence methodologies across cornerswhich includes sanity...

Job Description:At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software...

Hiring for STA Engineer4+ years of experience in STA at IP or SoC level using Primetime- Must be good in scripting, primarily tcl- Good understanding of Hardmacro development cycle and STA collaterals- Experience in DDR IP development, SerDes IP Development and Testchip development is a plus- Must be good in digital design concepts and understanding of...

Hiring for STA Engineer4+ years of experience in STA at IP or SoC level using Primetime- Must be good in scripting, primarily tcl- Good understanding of Hardmacro development cycle and STA collaterals- Experience in DDR IP development, SerDes IP Development and Testchip development is a plus- Must be good in digital design concepts and understanding of...

- ACL Digital is hiring for PD and STA Engineers for Bangalore and Location.- 3+years of experience in Physical Design.- Must have exp into floorplanning, STA blocks (2 blocks each) from synthesis, PnR, Timing and PV closure.- Notice period- Immediate to 30 days

SoC level – Static timing Analysis EngineerExperience : 10+ years of relevant experienceExpectations:Candidate should have strong STA fundamentals.Has done timing sign-off including timing margin calculations independently on SoC level.Experience in handling STA of multi-power domain designs.STA flow enhancement, abstraction with bottleneck...

So C Level-Static Timing Analysis6+years of relevant experience.Candidate should have strong STA fundamentals.Has done timing sign-off including timing margin calculations independently on So C Level.Experience in handling STA of multi-power domain/designs.STA flow enhancement, abstraction and bottleneck identification.proficient in design margins and SDC...

SoC Level-Static Timing Analysis6+years of relevant experience.Candidate should have strong STA fundamentals.Has done timing sign-off including timing margin calculations independently on SoC Level.Experience in handling STA of multi-power domain/designs.STA flow enhancement, abstraction and bottleneck identification.proficient in design margins and SDC...

Key ResponsibilitiesConducting research and development activities related to Thermal and material characterizationDesign and perform experiments for characterization and testing of materialsUtilize various characterization techniques such as TGA, DSC, STA, DMA and TMAAnalyze and interpret experimental data to draw meaningful conclusionsCollaborate with...

Job title: Sr Lead DFT EngineerLocation: Bangalore, IndiaDescriptionPrimary Responsibilities:Support and work closely with automotive customers (with special emphasis on in-system test using LBIST & MBIST) and non-automotive customers in defining DFT requirements and specifications for the ASICDevelopment and Implementation of DFT ArchitectureDesign and...

Senior Lead DFT Engineer – Bangalore, IndiaDescriptionWe are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience,...

SoC Level-Static Timing Analysis6+years of relevant experience.Candidate should have strong STA fundamentals.Has done timing sign-off including timing margin calculations independently on SoC Level.Experience in handling STA of multi-power domain/designs.STA flow enhancement, abstraction and bottleneck identification.proficient in design margins and SDC...

Job Title: Physical Design Engineer Location: Bangalore/ HyderabadJob Summary:We are seeking a skilled and detail-oriented Physical Design Engineer to work on the physical implementation of complex ASICs and SoCs. The role involves performing various backend design tasks, including floorplanning, placement, routing, timing closure, and power...

Job Title: Physical Design EngineerLocation: Bangalore/ HyderabadJob Summary:We are seeking a skilled and detail-oriented Physical Design Engineer to work on the physical implementation of complex ASICs and SoCs. The role involves performing various backend design tasks, including floorplanning, placement, routing, timing closure, and power optimization,...

Role : STA Lead Exp : 7+ yearsLocation : BangaloreBE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical DesignDetailed knowledge of EDA tools and flows, Tempus/Primetime experience is mustWell versed with the timing closure (STA), timing closure methodologiesPre/Post-layout constraint development to timing closureHandshake with the design team...

L&T Technologies (LTTS) is looking for Physical Design Engineers (PnR)with 4.5+ Years of experience.Job Location : BangalorePlease find the detailed job description below ::• IP/Block level PnR activities from Netlist to GDS-II.• Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like...

Dear CandidateWe, Cyient is hiring for ASIC RTL Design Engineer (Offshore-Onshore Model based Global Product Solution) Position.Base Location: BangaloreExperience Range: 3-5 YearsJob Description:Good understanding of Verilog and design conceptsHands on experience in RTL coding and verificationGood debugging skillsScripting experience is a plusHands on...