Senior Lead DFT Engineer

1 month ago

Delhi, India Mulya Technologies Full time
Senior Lead DFT Engineer – Bangalore, India

Description

We are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities.

We are seeking a Lead DFT Engineer for the R&D team based out of our Bangalore, India Office. This position is a hands-on technical position, working closely with the customer, design, and implementation teams.

Primary Responsibilities:

Support and work closely with automotive customers (with special emphasis on in-system test using LBIST & MBIST) and non-automotive customers in defining DFT requirements and specifications for the ASIC

Development and Implementation of DFT Architecture

Design and Verification of DFT logic and components

Generation of structural test vectors, analysis, and coverage improvement

Generation of timing constraints for the various DFT modes

Work with implementation teams on DFT STA, logical, physical, and power issues

Support ATE team with test vector porting, diagnosis, and physical failure analysis

Necessary Qualifications:

BE/ME, BTech/MTech in Electrical Engineering, Computer Science, or related field

Minimum of 10 years hands-on work experience in ASIC DFT design. Experience in an SoC product development organization or in an ASIC vendor company along with customer facing experience preferable

Hands-on experience with DFT circuit insertion and validation for scan, at-speed, MBIST and Boundary scan

Experience with Industry standard DFT/ATPG EDA tools like Tessent/TestMax/Modus. Experience with simulators and waveform debug tools.

Strong knowledge of DFT methodologies, industrial standards, and practices

Strong working knowledge of Chip design, Verilog/System Verilog, and design verification

Experience with STA tools like Primetime, SDF generation and Gate-level simulations

Understanding and expert handling of Verilog HDL based Netlists, design libraries and Scripting (Perl/Tcl)

Contact:

Uday

Mulya Technologies

"Mining The Knowledge Community"

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