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Physical Verification Engineer
2 weeks ago
Role
- Translate requirements into layout specifics using our state-of-the-art EDA tools and flows.
- Work independently in different phases of the RTL2GDS flow along with PV and IR/EM.
- Take physical limitation of hierarchical deep sub-micron FinFET designs into account.
- Tap your experience to contribute significantly to the hierarchical SoC architecture definition and implementation of clocking architectures.
- Be a member of an expert network and drive innovation, methodology and flow topics in your domain for next generation SoC Development
You are best equipped for this task if you have:
- Bachelor's or Master's degree with specialization in VLSI design with 5+ yrs experience
- Hands-on experience in physical design and timing closure of SoCs
- Experience of industry standard tools for physical design and signoff
- Experience in scripting languages (shell, perl, tcl) and Make flow
- Must be a good team player and should have desire to learn and explore
We are 26 years old company catering to top notch companies catering to Semicon Industries, Telecom and System Software.
We are operating out of Delhi, Bengaluru and Hyderabad.
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