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Physical Design Verification CAD
3 weeks ago
Responsible for assembling of various design system into a full chip.
Perform design rule checking (DRC) to identify and resolve System-on-chip layout violations and ensure compliance with manufacturing rules and constraints.
Conduct layout versus schematic (LVS) verification to ensure the accuracy and consistency between full chip layout and schematic of the IC design.
Execute electrical rule check (ERC) to identify potential electrical issues and ensure the integrity of the design.
Perform antenna and electrostatic discharge (ESD) checks to prevent potential reliability, latch-up, leakage issues.
Collaborate with design and layout teams to address and resolve physical design issues and optimize the layout for manufacturability and reliability.
Contribute to the development and improvement of physical verification methodologies and flows.
Work closely with process technology teams to understand and address process-related challenges and constraints.
Participate in tape-out activities and ensure that the physical design meets the required quality and reliability standards for fabrication.
Requirement:
Bachelor/master’s degree in Electrical/Electronic Engineering / Computer Science or equivalent
With minimum 4 years of relevant experience
Solid understanding of physical design concepts, IC manufacturing processes, and semiconductor device physics.
Proficiency in using physical verification tools such as Calibre, IC Validator, or other industry-standard DRC/LVS tools.
Experience with scripting languages such as TCL, Perl, or Python for automation and tool customization.
Strong problem-solving skills and the ability to analyze and debug complex physical design issues.
Excellent communication and teamwork skills to collaborate effectively with cross-functional teams.
Familiarity with EDA (Electronic Design Automation) tools and design methodologies is a plus.
Proficient in UNIX (Linux) platforms
Strong communication skills, problem solving and analytical skills
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