Physical Verification Engineer
3 weeks ago
Job Description:
We are seeking a skilled Physical Verification Engineer with 5 - 12 years of experience to join our team.
The ideal candidate will have expertise in physical design implementation and signoff at the block level, particularly at 16/7nm technology nodes.
Key responsibilities include floor planning, clock tree synthesis (CTS), static timing analysis (STA), physical verification, and a basic understanding of timing constraints.
Additionally, familiarity with ICC2, Innovus, Calibre, Formality, and LEC toolsets is essential.
Key Responsibilities:
- Perform physical design implementation and signoff activities at the block level, focusing on 16/7nm technology nodes.
- Develop floor plans to optimize layout and achieve design goals.
- Implement clock tree synthesis (CTS) to ensure proper clock distribution and minimize clock skew.
- Conduct static timing analysis (STA) to validate timing constraints and meet timing closure requirements.
- Perform physical verification tasks to ensure design robustness and adherence to design rules.
- Maintain a basic understanding of timing constraints and their impact on physical design.
- Utilize ICC2, Innovus, Calibre, Formality, and LEC toolsets for design implementation, verification, and Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- Advanced degree preferred.
- 5 - 12 years of experience in physical design implementation and signoff.
- Expertise in physical design at the block level, particularly at 16/7nm technology nodes.
- Proficiency in floor planning, clock tree synthesis (CTS), and static timing analysis (STA).
- Experience with physical verification methodologies and tools.
- Basic understanding of timing constraints and their impact on physical design.
- Good exposure to ICC2, Innovus, Calibre, Formality, and LEC toolsets.
- Strong analytical and problem-solving skills.
- Excellent communication and teamwork abilities.
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