Physical Verification Engineer

The group is part of Seagate’s VLSI Organization spread globally across multiple sites. Seagate designs world class controller SoCs for their HDDs. The group is responsible for the development of full custom ASICs for leading edge storage solutions. About the role - you will: • Work closely in the Design Implementation team for physical design,...

The group is part of Seagate’s VLSI Organization spread globally across multiple sites. Seagate designs world class controller SoCs for their HDDs. The group is responsible for the development of full custom ASICs for leading edge storage solutions. About the role - you will: • Work closely in the Design Implementation team for physical...

Job Description:We are seeking a skilled Physical Verification Engineer with 5 - 12 years of experience to join our team. The ideal candidate will have expertise in physical design implementation and signoff at the block level, particularly at 16/7nm technology nodes. Key responsibilities include floor planning, clock tree synthesis (CTS), static timing...

Position Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...

Position Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have the opportunity to work on many varieties of...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...

Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales,...

Description The Role   Our MCU DV Engineer will work with multi-functional global teams to implement and verify next generation highly complex microprocessor-based SoC designs. Develop system-level and unit-level test plan for functional verification and performance verification, write test benches and coverage using System Verilog and UVM,...

Description The Role   Our MCU DV Engineer will work with multi-functional global teams to implement and verify next generation highly complex microprocessor-based SoC designs. Develop system-level and unit-level test plan for functional verification and performance verification, write test benches and coverage using System Verilog and UVM, write...

Required ASIC/RTL design verification engineerExperience:- 3-10 yrsNotice period:- immediate to 90 daysSalary:- as per companySkills- Strong knowledge of SV and UVMThe purpose of the role is to develop modules in the company's next generation of ASICs for Radioequipment and Radio Access Network compute.These modules perform advanced signal processing.This...

Required ASIC/RTL design verification engineer Experience:- 3-10 yrs Notice period:- immediate to 90 days Salary:- as per company Skills- Strong knowledge of SV and UVM The purpose of the role is to develop modules in the company's next generation of ASICs for Radio equipment and Radio Access Network compute. These modules perform advanced signal...

Job Title: Design Verification Engineer Location: Pune, India Experience: 5yrs to 15yrs Job Description: Expertise in SV-UVM, Testbench development from scratch RISC-V processor based verification experience Protocols experience - PCIe/CXL/UCIe/DDR/Ethernet

We are looking to hire strong verification engineers with a sharp understanding of CPU and interconnect architectures and workloads. NVIDIA makes some of the most sophisticated chips in the world and is solving problems, with its vast arsenal of CPUs, GPUs, and SW, in areas such as HPC, Automated driving, Medical imaging, and much more! We are seeking highly...

Job Title: Design Verification EngineerLocation: Pune, IndiaExperience: 5yrs to 15yrsJob Description:Expertise in SV-UVM, Testbench development from scratchRISC-V processor based verification experienceProtocols experience - PCIe/CXL/UCIe/DDR/Ethernet

Job Title: Design Verification EngineerLocation: Pune, IndiaExperience: 5yrs to 15yrsJob Description:Expertise in SV-UVM, Testbench development from scratchRISC-V processor based verification experienceProtocols experience - PCIe/CXL/UCIe/DDR/Ethernet

Job Title: Design Verification EngineerLocation: Pune, IndiaExperience: 5yrs to 15yrsJob Description:Expertise in SV-UVM, Testbench development from scratchRISC-V processor based verification experienceProtocols experience - PCIe/CXL/UCIe/DDR/Ethernet

Job Title: Design Verification Engineer Location: Pune, India Experience: 5yrs to 15yrs Job Description: Expertise in SV-UVM, Testbench development from scratch RISC-V processor based verification experience Protocols experience - PCIe/CXL/UCIe/DDR/Ethernet

Designation: Field Verification Executives **Salary**: Rs.100/ point of Address Verification. (Point means a place of address it could a residence or office/business place in case of self-employed). No fixed salary purely commission based on number of verification done. No travelling expenses. Job Description: Omega credit information is a premier due...