Design Verification Engineer

Job Title: Design Verification Engineer Location: Pune, India Experience: 5yrs to 15yrs Job Description: Expertise in SV-UVM, Testbench development from scratch RISC-V processor based verification experience Protocols experience - PCIe/CXL/UCIe/DDR/Ethernet

Job Title: Design Verification EngineerLocation: Pune, IndiaExperience: 5yrs to 15yrsJob Description:Expertise in SV-UVM, Testbench development from scratchRISC-V processor based verification experienceProtocols experience - PCIe/CXL/UCIe/DDR/Ethernet

Job Title: Design Verification EngineerLocation: Pune, IndiaExperience: 5yrs to 15yrsJob Description:Expertise in SV-UVM, Testbench development from scratchRISC-V processor based verification experienceProtocols experience - PCIe/CXL/UCIe/DDR/Ethernet

Job Title: Design Verification Engineer Location: Pune, India Experience: 5yrs to 15yrs Job Description: Expertise in SV-UVM, Testbench development from scratch RISC-V processor based verification experience Protocols experience - PCIe/CXL/UCIe/DDR/Ethernet

Description The Role   Our MCU DV Engineer will work with multi-functional global teams to implement and verify next generation highly complex microprocessor-based SoC designs. Develop system-level and unit-level test plan for functional verification and performance verification, write test benches and coverage using System Verilog and UVM, write...

Description The Role   Our MCU DV Engineer will work with multi-functional global teams to implement and verify next generation highly complex microprocessor-based SoC designs. Develop system-level and unit-level test plan for functional verification and performance verification, write test benches and coverage using System Verilog and UVM,...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have the opportunity to work on many varieties of...

**Job Title**: Test and Verification Designer **Job title**:Test and Verification Designer The Test and Verification Engineering team which is part of the Quality and Reliability engineering department of Innovation Engineering and is a diverse group of more than 20 technical experts. All have extensive experience in the field of test and verification...

Description The Role You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. You'll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. You'll also partner with other teams to accelerate post-silicon...

Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales,...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position RequirementsM.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)Experience : 3+ years sound knowledge of DDR4/5, LPDDR4/5 IP. Hands on design/verification experience on DDR protocol Exposure to...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position RequirementsM.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)Experience : 3+ years sound knowledge of DDR4/5, LPDDR4/5 IP. Hands on design/verification experience on DDR protocol Exposure to DDR...

Position Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...

Position Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Location : Pune Design Engineer II Experience in developing complex test bench in System Verilog using OVM/UVM methodology Experience in coding functional coverage and system verilog assertions. Experience validation of...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Location : Pune  Design Engineer II Experience in developing complex test bench in System Verilog using OVM/UVM methodology Experience in coding functional coverage and system verilog assertions. Experience validation of protocols such...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have the opportunity to work on many varieties of...

Job Title: Design Verification EngineerLocation: Pune, IndiaExperience: 5yrs to 15yrsJob Description:- Expertise in SV-UVM, Testbench development from scratch- RISC-V processor based verification experience- Protocols experience - PCIe/CXL/UCIe/DDR/Ethernet