Physical Verification Engineer

Job DescriptionTake the leadership role of developing and supporting block and full chip automated physical verification flows and scriptsPerform block and full-chip physical verification and work with the physical design team to close design issuesWork with the PD team to clean up all DRC/LVS/ESD/ERC/ANT violations and sign off PV for tapeoutsWork closely...

Job Description Take the leadership role of developing and supporting block and full chip automated physical verification flows and scripts Perform block and full-chip physical verification and work with the physical design team to close design issues Work with the PD team to clean up all DRC/LVS/ESD/ERC/ANT violations and sign off PV for tapeouts Work...

Physical Verification EngineerBangalore IndiaExperience Min 6+ yearsOwn physical convergence(DRC/LVS/ERC/softcheck/ ESD/PERC ) closure of a complex subsystem in PnR and calibre signoff tools.Strong scripting skills in calibre DesignRev - svrf scripting (Must) and tcl, Python/Perl(optional).Deep understanding on DRC, LVS, ERC, PERC runset files and...

mplementation with emphasis on Physical Verification & Hard macro/core finishing activities.Must have led and been primarily responsible for physical verification checks , fixing and sign-off.Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues....

Looking for Lead - Physical Verification EngineerLocation: Bengaluru Experience: 10+yrsAvailability: Immediate to 20 DaysSkill Set Required:DRC, LVS DFM, Antenna, Density Fill Routines and other Tape-out sign-off experience is a must.Experience using Synopsys ICC Tool Tape-out experience of multiple complex chips at 14 nm or below is required. Good knowledge...

Looking for Lead - Physical Verification Engineer Location: Bengaluru Experience: 10+yrs Availability: Immediate to 20 Days Skill Set Required: DRC, LVS DFM, Antenna, Density Fill Routines and other Tape-out sign-off experience is a must. Experience using Synopsys ICC Tool Tape-out experience of multiple complex chips at 14 nm or below is required. Good...

we are looking for Physical verification engineerLocation-BangaloreExp_2+ YearsSkill: PV,CaliberNP- Immediate to 15 Days

Looking for Lead Physical Verification Engineer Location: Bengaluru Experience: 10+yrs Availability: Immediate to 20 Days Skill Set Required: DRC, LVS DFM, Antenna, Density Fill Routines and other Tape-out sign-off experience is a must. Experience using Synopsys ICC Tool Tape-out experience of multiple complex chips at 14 nm or below is required. Good...

Job Description:Responsible for assembling of various design system into a full chip.Perform design rule checking (DRC) to identify and resolve System-on-chip layout violations and ensure compliance with manufacturing rules and constraints.Conduct layout versus schematic (LVS) verification to ensure the accuracy and consistency between full chip layout and...

Job Description:We are seeking a skilled Physical Verification Engineer with 5 - 12 years of experience to join our team. The ideal candidate will have expertise in physical design implementation and signoff at the block level, particularly at 16/7nm technology nodes. Key responsibilities include floor planning, clock tree synthesis (CTS), static timing...

Job Description:We are seeking a skilled Physical Verification Engineer with 5 - 12 years of experience to join our team. The ideal candidate will have expertise in physical design implementation and signoff at the block level, particularly at 16/7nm technology nodes. Key responsibilities include floor planning, clock tree synthesis (CTS), static timing...

Physical Verification EngineerBangalore IndiaExperience Min 6+ yearsOwn physical convergence(DRC/LVS/ERC/softcheck/ESD/PERC) closure of a complex subsystem in PnR and calibre signoff tools.Strong scripting skills in calibre DesignRev svrf scripting (Must) and tcl, Python/Perl(optional).Deep understanding on DRC, LVS, ERC, PERC runset files and signoff...

Company DescriptionNikSperri Technologies Private Limited is a technology company focused on providing high-end services and value to its customers in India and globally. With expertise in RTL Design, Integration, Verification, STA-Synthesis, Physical Design, and tapeout, NikSperri can execute complete design projects based on specifications or existing...

Company DescriptionNikSperri Technologies Private Limited is a technology company focused on providing high-end services and value to its customers in India and globally. With expertise in RTL Design, Integration, Verification, STA-Synthesis, Physical Design, and tapeout, NikSperri can execute complete design projects based on specifications or existing...

we are looking for Physical verification engineerLocation-BangaloreExp_2+ YearsSkill: PV,CaliberNP Immediate to 15 Days

Senior Verification Engineer Summary Experience Required: 6 - 12 YearsJob Term: PermanentLocation: BangaloreCategory: Semiconductor DesignA leading designer, developer and global supplier of a broad range of digital and analog semiconductor connectivity solutions that serve the wired infrastructure, wireless communications, enterprise storage and industrial...

IC design implementation from RTL to netlist including synthesis, timing constraint composing IC physical implementation from netlist to GDSII, including floor planning, power grid implementation, place and route, clock tree synthesis, timing ECO, design closure IC design verification including timing analysis, timing signoff, formal verification and low...

We are hiring for Physical Design role.Location: Bangalore/HyderabadExperience: 4+ years into Physical DesignHands-on work experience of at least 4 years, with project track record in advanced nodes upto 5nmDeep expertise of industry leading place and route, PV and other physical design toolsExperience in working in full chip or at block level, owning...

Job Title: Senior Physical Design EngineerLocation: Ahmedabad, Bangalore, Noida & HyderabadRoles and Responsibilities:Minimum 5 years experience in Physical Design is required.Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII,Block level Physical Verification,Block level Timing Signoff and ECO generation.Block level Power...

Layout Design Engineer (Analog / RF) About the Client : Our MNC semiconductor client provides high-performance IC products in IoT Radios, Timing and Audio Markets.They are looking for Layout Design Engineer (Analog / RF) to be based at Bangalore with the following : - Total 3 to 5 years of experience in Layout design engineering (Analog/RF).- Must have...